ATtiny261-ESSZ datasheet(94/227 Pages) ATMEL

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7753C–AVR–07/09

ATtiny261/ATtiny461/ATtiny861

16.2.3

Registers

The Timer/Counter (TCNT1) and Output Compare Registers (OCR1A, OCR1B, OCR1C and

OCR1D) are 8-bit registers that are used as a data source to be compared with the TCNT1 con-

tents. The OCR1A, OCR1B and OCR1D registers determine the action on the OC1A, OC1B and

OC1D pins and they can also generate the compare match interrupts. The OCR1C holds the

Timer/Counter TOP value, i.e. the clear on compare match value. The Timer/Counter1 High

Byte Register (TC1H) is a 2-bit register that is used as a common temporary buffer to access the

MSB bits of the Timer/Counter1 registers, if the 10-bit accuracy is used.

Interrupt request (overflow TOV1, and compare matches OCF1A, OCF1B, OCF1D and fault pro-

tection FPF1) signals are visible in the Timer Interrupt Flag Register (TIFR) and Timer/Counter1

Control Register D (TCCR1D). The interrupts are individually masked with the Timer Interrupt

Mask Register (TIMSK) and the FPIE1 bit in the Timer/Counter1 Control Register D (TCCR1D).

Control signals are found in the Timer/Counter Control Registers TCCR1A, TCCR1B, TCCR1C,

TCCR1D and TCCR1E.

16.2.4

Synchronization

In asynchronous clocking mode the Timer/Counter1 and the prescaler allow running the CPU

from any clock source while the prescaler is operating on the fast peripheral clock (PCK) having

frequency of 64 MHz (or 32 MHz in Low Speed Mode). This is possible because there is a syn-

chronization boundary between the CPU clock domain and the fast peripheral clock domain.

Figure 16-2 shows Timer/Counter 1 synchronization register block diagram and describes syn-

chronization delays in between registers. Note that all clock gating details are not shown in the

figure.

The Timer/Counter1 register values go through the internal synchronization registers, which

cause the input synchronization delay, before affecting the counter operation. The registers

TCCR1A, TCCR1B, TCCR1C, TCCR1D, OCR1A, OCR1B, OCR1C and OCR1D can be read

back right after writing the register. The read back values are delayed for the Timer/Counter1

(TCNT1) register, Timer/Counter1 High Byte Register (TC1H) and flags (OCF1A, OCF1B,

OCF1D and TOV1), because of the input and output synchronization.

The system clock frequency must be lower than half of the PCK frequency, because the syn-

chronization mechanism of the asynchronous Timer/Counter1 needs at least two edges of the

PCK when the system clock is high. If the frequency of the system clock is too high, it is a risk

that data or control values are lost.

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