ATtiny261-ESSZ datasheet(88/227 Pages) ATMEL

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7753C–AVR–07/09

ATtiny261/ATtiny461/ATtiny861

14.10.7

TIFR – Timer/Counter0 Interrupt Flag Register

• Bit 4– OCF0A: Output Compare Flag 0 A

The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data

in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor-

responding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),

and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.

The OCF0A is also set in 16-bit mode when a Compare Match occurs between the Timer/Coun-

ter and 16-bit data in OCR0B/A. The OCF0A is not set in Input Capture mode when the Output

Compare Register OCR0A is used as an Input Capture Register.

• Bit 3 – OCF0B: Output Compare Flag 0 B

The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in

OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the cor-

responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),

and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.

The OCF0B is not set in 16-bit Output Compare mode when the Output Compare Register

OCR0B is used as the high byte of the 16-bit Output Compare Register or in 16-bit Input Cap-

ture mode when the Output Compare Register OCR0B is used as the high byte of the Input

Capture Register.

• Bit 1 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware

when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by

writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt

Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.

• Bits 0 – ICF0: Timer/Counter0, Input Capture Flag

This flag is set when a capture event occurs on the ICP0 pin. When the Input Capture Register

(ICR0) is set to be used as the TOP value, the ICF0 flag is set when the counter reaches the

TOP value.

ICF0 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,

ICF0 can be cleared by writing a logic one to its bit location.

Bit

76543210

0x38 (0x58)

OCF1D

OCF1A

OCF1B

OCF0A

OCF0B

TOV1

TOV0

ICF0

TIFR

Read/Write

R/W

Initial Value

00000000

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