ATtiny261-ESSZ datasheet(86/227 Pages) ATMEL

86 / 227 page

7753C–AVR–07/09

ATtiny261/ATtiny461/ATtiny861

Modes of operation supported by the Timer/Counter unit are: Normal mode (counter) and Clear

Timer on Compare Match (CTC) mode (see “Modes of Operation” on page 75).

14.10.2

TCNT0L – Timer/Counter0 Register Low Byte

The Timer/Counter0 Register Low Byte, TCNT0L, gives direct access, both for read and write

operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0L Register blocks (dis-

ables) the Compare Match on the following timer clock. Modifying the counter (TCNT0L) while

the counter is running, introduces a risk of missing a Compare Match between TCNT0L and the

OCR0x Registers. In 16-bit mode the TCNT0L register contains the lower part of the 16-bit

Timer/Counter0 Register.

14.10.3

TCNT0H – Timer/Counter0 Register High Byte

When 16-bit mode is selected (the TCW0 bit is set to one) the Timer/Counter Register TCNT0H

combined to the Timer/Counter Register TCNT0L gives direct access, both for read and write

operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes

are read and written simultaneously when the CPU accesses these registers, the access is per-

formed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by

all the other 16-bit registers. See “Accessing Registers in 16-bit Mode” on page 81

14.10.4

OCR0A – Timer/Counter0 Output Compare Register A

The Output Compare Register A contains an 8-bit value that is continuously compared with the

counter value (TCNT0L). A match can be used to generate an Output Compare interrupt.

In 16-bit mode the OCR0A register contains the low byte of the 16-bit Output Compare Register.

To ensure that both the high and the low bytes are written simultaneously when the CPU writes

to these registers, the access is performed using an 8-bit temporary high byte register (TEMP).

This temporary register is shared by all the other 16-bit registers. See “Accessing Registers in

16-bit Mode” on page 81.

14.10.5

OCR0B – Timer/Counter0 Output Compare Register B

The Output Compare Register B contains an 8-bit value that is continuously compared with the

counter value (TCNT0L in 8-bit mode and TCNTH in 16-bit mode). A match can be used to gen-

erate an Output Compare interrupt.

Bit

76543210

0x32 (0x52)

TCNT0L[7:0]

TCNT0L

Read/Write

R/W

Initial Value

00000000

Bit

76543210

0x14 (0x34)

TCNT0H[7:0]

TCNT0H

Read/Write

R/W

Initial Value

00000000

Bit

76543210

0x13 (0x33)

OCR0A[7:0]

OCR0A

Read/Write

R/W

Initial Value

00000000

Bit

76543210

0x12 (0x32)

OCR0B[7:0]

OCR0B

Read/Write

R/W

Initial Value

00000000

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