ATtiny261-ESSZ datasheet(75/227 Pages) ATMEL

75 / 227 page

7753C–AVR–07/09

ATtiny261/ATtiny461/ATtiny861

The counter is incremented at each timer clock (clk

T0) until it passes its TOP value and then

restarts from BOTTOM. The counting sequence is determined by the setting of the CTC0 bit

located in the Timer/Counter Control Register (TCCR0A). For more details about counting

sequences, see “Modes of Operation” on page 75. clk

T0 can be generated from an external or

internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is

selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the

CPU, regardless of whether clk

T0 is present or not. A CPU write overrides (has priority over) all

counter clear or count operations. The Timer/Counter Overflow Flag (TOV0) is set when the

counter reaches the maximum value and it can be used for generating a CPU interrupt.

14.5

Modes of Operation

The mode of operation is defined by the Timer/Counter Width (TCW0), Input Capture Enable

(ICEN0) and Wave Generation Mode (CTC0) bits in “TCCR0A – Timer/Counter0 Control Regis-

ter A” on page 85. Table 14-3 shows the different Modes of Operation.

14.5.1

Normal 8-bit Mode

In the Normal 8-bit mode, see Table 14-3 on page 75, the counter (TCNT0L) is incrementing

until it overruns when it passes its maximum 8-bit value (MAX = 0xFF) and then restarts from the

bottom (0x00). The Overflow Flag (TOV0) will be set in the same timer clock cycle as the

TCNT0L becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only

set, not cleared. However, combined with the timer overflow interrupt that automatically clears

the TOV0 Flag, the timer resolution can be increased by software. There are no special cases to

consider in the Normal 8-bit mode, a new counter value can be written anytime. The Output

Compare Unit can be used to generate interrupts at some given time.

14.5.2

Clear Timer on Compare Match (CTC) 8-bit Mode

In Clear Timer on Compare or CTC mode, see Table 14-3 on page 75, the OCR0A Register is

used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the

counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter,

hence also its resolution. This mode allows greater control of the Compare Match output fre-

quency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 14-2. The counter value (TCNT0)

increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter

(TCNT0) is cleared.

Table 14-3.

Modes of operation

Mode

ICEN0

TCW0

CTC0

Mode of Operation

TOP Value

Update of OCRx at

TOV Flag Set on

0000

Normal 8-bit Mode

0xFF

Immediate

MAX (0xFF)

1001

8-bit CTC

OCR0A

Immediate

MAX (0xFF)

16-bit Mode

0xFFFF

Immediate

MAX (0xFFFF)

8-bit Input Capture Mode

0xFF

Immediate

MAX (0xFF)

16-bit Input Capture Mode

0xFFFF

Immediate

MAX (0xFFFF)

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