ATtiny261-ESSZ datasheet(28/227 Pages) ATMEL

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7753C–AVR–07/09

ATtiny261/ATtiny461/ATtiny861

Figure 7-3.

External Clock Drive Configuration

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 7-3.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal

clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page

32 for details.

7.5

High Frequency PLL Clock - PLL

CLK

There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator

for the use of the Peripheral Timer/Counter1 and for the system clock source. When selected as

a system clock source, by programming the CKSEL fuses to ‘0001’, it is divided by four like

shown in Table 7-4. When this clock source is selected, start-up times are determined by the

SUT fuses as shown in Table 7-5. See also “PCK Clocking System” on page 26.

Table 7-3.

Start-up Times for the External Clock Selection

SUT1..0

Start-up Time from

Power-down and Power-save

Additional Delay from

Reset

Recommended Usage

6 CK

14CK

BOD enabled

6 CK

14CK + 4 ms

Fast rising power

6 CK

14CK + 64 ms

Slowly rising power

Reserved

EXTERNAL

CLOCK

SIGNAL

CLKI

GND

Table 7-4.

PLLCK Operating Modes

CKSEL3..0

Nominal Frequency

0001

16 MHz

Table 7-5.

Start-up Times for the PLLCK

SUT1..0

Start-up Time from Power

Down

Additional Delay from

Power-On-Reset (VCC = 5.0V) Recommended usage

14CK + 1K (1024) + 4 ms

4 ms

BOD enabled

14CK + 16K (16384) + 4 ms

4 ms

Fast rising power

14CK + 1K (1024) + 64 ms

4 ms

Slowly rising power

14CK + 16K (16384) + 64 ms

4 ms

Slowly rising power

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