ATtiny261-ESSZ datasheet(103/227 Pages) ATMEL

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103

7753C–AVR–07/09

ATtiny261/ATtiny461/ATtiny861

The Timer/Counter Overflow Flag (TOV1) is set in the same clock cycle as the TCNT1 becomes

zero. The TOV1 Flag in this case behaves like a 11th bit, except that it is only set, not cleared.

However, combined with the timer overflow interrupt, that automatically clears the TOV1 Flag,

the timer resolution can be increased by software. There are no special cases to consider in the

Normal mode, a new counter value can be written anytime.

The Output Compare Unit can be used to generate interrupts at some given time. Using the Out-

put Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time. For generating a waveform, the OCW1x output can be set to

toggle its logical level on each Compare Match by setting the Compare Output mode bits to tog-

gle mode (COM1x1:0 = 1). The OC1x value will not be visible on the port pin unless the data

direction for the pin is set to output. The waveform generated will have a maximum frequency of

OC1x = fclkT1/4 when OCR1C is set to zero. The waveform frequency is defined by the following

equation:

Resolution shows how many bit is required to express the value in the OCR1C register. It is cal-

culated by following equation:

Resolution

PWM = log2(OCR1C + 1).

The Output Compare Pin configurations in Normal Mode are described in Table 16-2.

16.7.2

Fast

PWM Mode

The fast Pulse Width Modulation or fast PWM mode (PWM1x = 1 and WGM10 = 0) provides a

high frequency PWM waveform generation option. The fast PWM differs from the other PWM

option by its single-slope operation. The counter counts from BOTTOM to TOP (defined as

OCR1C) then restarts from BOTTOM. In non-inverting Compare Output mode the Waveform

Output (OCW1x) is cleared on the Compare Match between TCNT1 and OCR1x and set at

BOTTOM. In inverting Compare Output mode, the Waveform Output is set on Compare Match

and cleared at BOTTOM. In complementary Compare Output mode the Waveform Output is

cleared on the Compare Match and set at BOTTOM.

Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice

as high as the Phase and Frequency Correct PWM mode that use dual-slope operation. This

high frequency makes the fast PWM mode well suited for power regulation, rectification, and

DAC applications. High frequency allows physically small sized external components (coils,

capacitors), and therefore reduces total system cost.

The timing diagram for the fast PWM mode is shown in Figure 16-11. The counter is incre-

mented until the counter value matches the TOP value. The counter is then cleared at the

following timer clock cycle. The TCNT1 value is in the timing diagram shown as a histogram for

illustrating the single-slope operation.

Table 16-2.

Output Compare Pin Configurations in Normal Mode

COM1x1

COM1x0

OC1x Pin

Disconnected

OC1x

Disconnected

OC1x

Disconnected

OC1x

fOC1x

clkT1

OCR1C

()

⋅

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