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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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ATtiny261-ESSZ Scheda tecnica(PDF) 195 Page - ATMEL Corporation |
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ATtiny261-ESSZ Scheda tecnica(HTML) 195 Page - ATMEL Corporation |
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195 / 227 page  195 7753C–AVR–07/09 ATtiny261/ATtiny461/ATtiny861 Figure 23-5. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1) Note: 1. The timing requirements shown in Figure 23-3 (i.e., tDVXH, tXHXL, and tXLDX) also apply to read- ing operation. Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. 2. t WLRH_CE is valid for the Chip Erase command. Table 23-7. Parallel Programming Characteristics, V CC = 5V ± 10% Symbol Parameter Min Typ Max Units VPP Programming Enable Voltage 11.5 12.5 V IPP Programming Enable Current 250 µA tDVXH Data and Control Valid before XTAL1 High 67 ns tXLXH XTAL1 Low to XTAL1 High 200 ns tXHXL XTAL1 Pulse Width High 150 ns tXLDX Data and Control Hold after XTAL1 Low 67 ns tXLWL XTAL1 Low to WR Low 0 ns tBVPH BS1 Valid before PAGEL High 67 ns tPHPL PAGEL Pulse Width High 150 ns tPLBX BS1 Hold after PAGEL Low 67 ns tWLBX BS2/1 Hold after WR Low 67 ns tPLWL PAGEL Low to WR Low 67 ns tBVWL BS1 Valid to WR Low 67 ns tWLWH WR Pulse Width Low 150 ns tWLRL WR Low to RDY/BSY Low 0 1 µs tWLRH WR Low to RDY/BSY High (1) 3.7 4.5 ms tWLRH_CE WR Low to RDY/BSY High for Chip Erase (2) 7.5 9 ms tXLOL XTAL1 Low to OE Low 0 ns tBVDV BS1 Valid to DATA valid 0 250 ns tOLDV OE Low to DATA Valid 250 ns tOHDZ OE High to DATA Tri-stated 250 ns XTAL1 OE ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) DATA PAGEL/BS1 XA0 XA1/BS2 LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) t BVDV t OLDV t XLOL t OHDZ |
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