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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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WM8953ECS/RV Scheda tecnica(PDF) 42 Page - Wolfson Microelectronics plc |
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WM8953ECS/RV Scheda tecnica(HTML) 42 Page - Wolfson Microelectronics plc |
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42 / 100 page  WM8953 Production Data w PD, January 2009, Rev 4.0 42 GPIO CONTROL REGISTERS Register bit AIF_TRIS, when set, tri-states all audio interface and GPIO pins. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R9 (09h) 13 AIF_TRIS 0b Audio Interface and GPIO Tristate 0 = Audio interface and GPIO pins operate normally 1 = Tristate all audio interface and GPIO pins Table 20 GPIO and GPI Pin Function Select The GPIO pins are also controlled by the register fields described in Table 21. Note the order of precedence described earlier applies. Pull-up and pull-down resistors may be enabled on any of GPIO3, GPIO4 or GPIO5. If enabled, these settings take precedence over all other GPIO selections for that pin. Note that, by default, the pull-down resistors on GPIO3, GPIO4 and GPIO5 are enabled. When the GPIO pins are used as inputs, de-bounce and interrupt masking may be controlled on all GPIO pins (including GPI7 and GPI8) using GPIOn_DEB_ENA and GPIOn_IRQ_ENA bits as shown in Table 22. For each of GPIO3, GPIO4 and GPIO5, the register field GPIOn_SEL is used to select the pin functions of the individual GPIO pins as shown in Table 22. Note that this control has the lowest precedence and is only effective when GPIOn_PU, GPIOn_PD and AIF_TRIS are set to allow GPIO functionality on that GPIO pin. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 15 GPIO4_DEB_ENA 0b 14 GPIO4_IRQ_ENA 0b 13 GPIO4_PU 0b 12 GPIO4_PD 1b 11:8 GPIO4_SEL[3:0] 0000b See Table 22 for GPIO4 control bit description 7 GPIO3_DEB_ENA 0b 6 GPIO3_IRQ_ENA 0b 5 GPIO3_PU 0b 4 GPIO3_PD 1b R20 (14h) 3:0 GPIO3_SEL[3:0] 0000b See Table 22 for GPIO3 control bit description 7 GPIO5_DEB_ENA 0b 6 GPIO5_IRQ_ENA 0b 5 GPIO5_PU 0b 4 GPIO5_PD 1b R21 (15h) 3:0 GPIO5_SEL[3:0] 0000b See Table 22 for GPIO5 control bit description 7 GPI8_DEB_ENA 0b 6 GPI8_IRQ_ENA 0b 4 GPI8_ENA 0b See Table 22 for GPIn control bit description 3 GPI7_DEB_ENA 0b 2 GPI7_IRQ_ENA 0b R22 (16h) 0 GPI7_ENA 0b See Table 22 for GPIn control bit description Table 21 GPIO and GPI Control |
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