WM8953ECSSLASHRV datasheet(67/100 Pages) WOLFSON

67 / 100 page

Production Data

WM8953

PD, January 2009, Rev 4.0

CLOCKING AND SAMPLE RATES

The internal clocks for the ADCs, DSP core functions and digital audio interface are derived from a

common internal clock source, SYSCLK.

SYSCLK can either be derived directly from MCLK, or may be generated from a PLL using MCLK as

an external reference. Many commonly-used audio sample rates can be derived directly from typical

MCLK frequencies; the PLL provides additional flexibility for a wide range of MCLK frequencies. All

clock configurations must be set up before enabling playback to avoid glitches.

The ADC sample rate is selectable, relative to SYSCLK, using ADC_CLKDIV. This must be set

according to the required sampling frequency and depending on the selected clocking mode

(AIF_LRCLKRATE).

In master mode, BCLK is also derived from SYSCLK via a programmable division set by BCLK_DIV.

The BCLK frequency must be set appropriately to support the sample rate of the ADC. The ADCLRC

signal does not automatically match the ADC sample rate; this must be configured using

ADCLRC_RATE as described under “Digital Audio Interface Control”.

A clock (OPCLK) derived from SYSCLK can be output on the GPIO pins to provide clocking for other

parts of the system. This clock is enabled by OPCLK_ENA and its frequency is set by OPCLKDIV.

A slow clock (TOCLK) derived from SYSCLK can be used to de-bounce the button/accessory detect

inputs, and to set the timeout period for volume updates when zero-cross detect is used. This clock

is enabled by TOCLK_ENA and its frequency is set by TOCLK_RATE.

Table 38 to Table 43 show the clocking and sample rate controls for MCLK input, BCLK output (in

master mode), ADCs, and GPIO clock output.

The overall clocking scheme for the WM8953 is illustrated in Figure 50.

MCLK

PLL

R=f2/f1

SYSCLK

MASTER

MODE

CLOCK

OUTPUTS

fPLLOUT

f/N

f/4

f/2

GPIO Clock Output

f/N

Timeout and

De-Bounce

Clock

Button/accessory detect de-bounce,

Volume update timeout

TOCLK_ENA

f/221

f/219

MCLK

MCLK is the master clock source

SYSCLK

All internal clocks are derived from SYSCLK.

SYSCLK can be derived directly from MCLK or from the PLL output.

It has a programmable divide by 2 option (MCLKDIV).

ADC_CLKDIV

ADC sample rate is set by ADC_CLKDIV (Master or slave mode).

ADCLRC_RATE

ADCLRC in master mode is derived from BCLK and is controlled by ADCLRC_RATE.

BCLK_DIV

BCLK rate is set by BCLK_DIV in master mode.

The BCLK rate should be high enough to support the selected ADC sample rate.

OPCLKDIV

GPIO Clock output frequency is set by OPCLKDIV.

TOCLK_RATE

A slow clock is used for button/accessory detect de-bounce and for volume update

timeouts (when zero-cross detect is enabled). The frequency of this slow clock is set by

TOCLK_RATE.

TOCLK_RATE

BCLK_DIV[3:0]

0000 = SYSCLK

0001 = SYSCLK / 1.5

0010 = SYSCLK / 2

0011 = SYSCLK / 3

0100 = SYSCLK / 4

0101 = SYSCLK / 5.5

0110 = SYSCLK / 6

0111 = SYSCLK / 8

1000 = SYSCLK / 11

1001 = SYSCLK / 12

1010 = SYSCLK / 16

1011 = SYSCLK / 22

1100 = SYSCLK / 24

1101 = SYSCLK / 32

1110 = SYSCLK / 44

1111 = SYSCLK / 48

BCLKDIV

[3:0]

OPCLKDIV[3:0]

0000 = SYSCLK

0001 = SYSCLK / 2

0010 = SYSCLK / 3

0011 = SYSCLK / 4

0100 = SYSCLK / 5.5

0101 = SYSCLK / 6

0110 = SYSCLK / 8

0111 = SYSCLK / 12

1000 = SYSCLK /16

1001 – 1111 = Reserved

OPCLKDIV

MCLKDIV[1:0]

00 = MCLK

01 = Reserved

10 = MCLK / 2

11 = Reserved

MCLKDIV[1:0]

SYSCLK_SRC

PRESCALE

ADC_CLKDIV[2:0]

000 = SYSCLK

001 = SYSCLK / 1.5

010 = SYSCLK / 2

011 = SYSCLK / 3

100 = SYSCLK / 4

101 = SYSCLK / 5.5

110 = SYSCLK / 6

111 = Reserved

OPCLK_ENA

BCLK

ADCLRC

f/N

ADCLRC_RATE

[10:0]

MCLK_INV

256fs

ADC_CLKDIV

[2:0]

f/4

ADC DSP

64fs

f/N

ADC

f/N

Figure 50 Clocking Scheme

WM8953ECS/RV Scheda tecnica(PDF) 67 Page - Wolfson Microelectronics plc

WM8953ECS/RV Scheda tecnica(HTML) 67 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Scheda tecnica Scarica

Link URL