WM8953ECSSLASHRV datasheet(72/100 Pages) WOLFSON

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WM8953

Production Data

PD, January 2009, Rev 4.0

TOCLK CONTROL

A slow clock (TOCLK) is derived from SYSCLK to enable input de-bouncing and volume update

timeout functions. This clock is enabled by register bit TOCLK_ENA, and its frequency is controlled

by TOCLK_RATE, as described in Table 43.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

TOCLK_RATE

Timeout Clock Rate

(Selects clock to be used for volume

update timeout and GPIO input de-

bounce)

0 = SYSCLK / 221 (Slower Response)

1 = SYSCLK / 219 (Faster Response)

R6 (06h)

TOCLK_ENA

Timeout Clock Enable

(This clock is required for volume update

timeout and GPIO input de-bounce)

0 = disabled

1 = enabled

Table 43 TOCLK Control

USB MODE

It is possible to reduce power consumption by disabling the PLL in some applications. One such

application is when SYSCLK is generated from a 12MHz USB clock source. Setting the

AIF_LRCLKRATE bit as described earlier (see “ADC Sample Rates”) allows a sample rate close to

44.1kHz to be generated with no additional PLL power consumption.

In this configuration, SYSCLK must be driven directly from MCLK and by disabling the PLL. This is

achieved by setting SYSCLK_SRC=0, PLL_ENA=0.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R10 (0Ah)

AIF_LRCLKRATE

LRCLK Rate

0 = Normal mode (256 * fs)

1 = USB mode (272 * fs)

Table 44 USB Mode Control

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