WM8953ECSSLASHRV datasheet(69/100 Pages) WOLFSON

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Production Data

WM8953

PD, January 2009, Rev 4.0

ADC SAMPLE RATE

The ADC sample rate is selectable, relative to SYSCLK, by setting the register fields ADC_CLKDIV.

This must be set according to the SYSCLK frequency, and according to the selected clocking mode.

Two clocking modes are provided - Normal Mode (AIF_LRCLKRATE = 0) allows selection of the

commonly used sample rates from typical audio system clocking frequencies (eg. 12.288MHz); USB

Mode (AIF_LRCLKRATE = 1) allows many of these sample rates to be generated from a 12MHz

USB clock. Depending on the available clock sources, the USB mode may be used to save power by

supporting 44.1kHz operation without requiring the PLL.

The AIF_LRCLKRATE field must be set as described in Table 39 to ensure correct operation of

internal functions according to the SYSCLK / Fs ratio. Table 40 describes the available sample rates

using four different common MCLK frequencies.

In Normal mode, the programmable division set by ADC_CLKDIV must ensure that a 256 * ADC Fs

clock is generated for the ADC DSP.

In USB mode, the programmable division set by ADC_CLKDIV must ensure that a 272 * ADC Fs

clock is generated for the ADC DSP.

Note that in USB mode, the ADC sample rates do not match exactly with the commonly used sample

rates (e.g. 44.118 kHz instead of 44.100 kHz). At most, the difference is less than 0.5%. Data

recorded at 44.100 kHz sample rate and replayed at 44.118 kHz will experience a slight (sub 0.5%)

pitch shift as a result of this difference. Note also that the USB mode cannot be used to generate a

48kHz samples rate from a 12MHz MCLK; the PLL should be used in this case.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R7 (07h)

7:5

ADC_CLKDIV

[2:0]

000b

ADC Sample Rate Divider

000 = SYSCLK / 1.0

001 = SYSCLK / 1.5

010 = SYSCLK / 2.0

011 = SYSCLK / 3.0

100 = SYSCLK / 4.0

101 = SYSCLK / 5.5

110 = SYSCLK / 6.0

111= Reserved

R10 (0Ah)

AIF_LRCLKRAT

LRCLK Rate

0 = Normal mode (256 * fs)

1 = USB mode (272 * fs)

Table 39 ADC Sample Rate Control

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