WM8953ECSSLASHRV datasheet(64/100 Pages) WOLFSON

Il numero della parte	WM8953ECS/RV

Spiegazioni elettronici	Low Power Stereo ADC with PLL and TDM Interface

PDF	100 Pages

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Produttore elettronici	WOLFSON [Wolfson Microelectronics plc]

Homepage	http://www.wolfsonmicro.com

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64 / 100 page

WM8953

Production Data

PD, January 2009, Rev 4.0

MASTER MODE BCLK AND ADCLRC ENABLE

The audio interface pins BCLK, ADCLRC and ADCDAT can be independently programmed to

operate in master mode or slave mode using register bit AIF_MSTR.

When the audio interface is operating in slave mode, the BCLK and ADCLRC clock outputs to these

pins are by default disabled to allow the digital audio source to drive these pins.

It is also possible to force the ADCLRC to be output using register bit ADCLRC_DIR, allowing mixed

master and slave mode.

The clock generators for the audio interface are enabled according to the control signals shown in

Figure 47.

Figure 47 Clock Output Control

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

AIF_MSTR

Audio Interface Master Mode Select

0 = Slave mode

1 = Master mode

ADCLRC_DIR

ADCLRC Direction

(Forces ADCLRC clock to be output in

slave mode)

0 = ADCLRC normal operation

1 = ADCLRC clock output enabled

R8 (08h)

10:0

ADCLRC_RATE

[10:0]

040h

ADCLRC Rate

ADCLRC clock output = BCLK /

ADCLRC_RATE

Integer (LSB = 1)

Valid from 8..2047

Table 35 Digital Audio Interface Clock Output Control

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