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WM8953ECS/RV Scheda tecnica(PDF) 11 Page - Wolfson Microelectronics plc

Il numero della parte WM8953ECS/RV
Spiegazioni elettronici  Low Power Stereo ADC with PLL and TDM Interface
PDF  100 Pages
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Produttore elettronici  WOLFSON [Wolfson Microelectronics plc]
Homepage  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8953ECS/RV Scheda tecnica(HTML) 11 Page - Wolfson Microelectronics plc

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Production Data
WM8953
w
PD, January 2009, Rev 4.0
11
Test Conditions
DCVDD = 1.8V, DBVDD = 3.3V, AVDD = 3.3V, TA = +25
oC, 1kHz signal, fs = 48kHz,
PGA gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analogue Reference Levels
VMID Midrail Reference Voltage
-3%
AVDD/2
+3%
V
Microphone Bias
3mA load current
MBSEL=0
-5%
0.9
×AVDD
+5%
V
Bias Voltage
3mA load current
MBSEL=1
-5%
0.65
×AVDD
+5%
V
Bias Current Source
3
mA
Output Noise Density
1kHz to 20kHz
100
nV/
√Hz
AVDD PSRR (217Hz)
100mV pk-pk @217Hz
on AVDD
45
dB
Digital Input / Output
Input HIGH Level
0.7
×DBVDD
V
Input LOW Level
0.3
×DBVDD
V
Note that digital input pins should not be left unconnected / floating.
Internal pull-up/pull-down resistors may be enabled on GPIO3, GPIO4 and GPIO5 if required.
Output HIGH Level
IOL=1mA
0.9
×DBVDD
V
Output LOW Level
IOH=-1mA
0.1
×DBVDD
V
Input capacitance
10
pF
Input leakage
-0.9
0.9
uA
PLL
PRESCALE = 0b
7.7
18
MHz
Input Frequency
PRESCALE = 1b
14.4
36
MHz
Lock time
200
us
GPIO
SYSCLK=MCLK;
OPCLKDIV=0000
35
65
%
SYSCLK=MCLK;
OPCLKDIV=1000
45
55
%
SYSCLK=PLL output;
OPCLKDIV=0000
45
55
%
Clock output duty cycle
(Integer OPCLKDIV)
SYSCLK=PLL output;
OPCLKDIV=1000
45
55
%
SYSCLK=MCLK;
OPCLKDIV=0100
33
66
%
Clock output duty cycle
(Non-integer OPCLKDIV)
SYSCLK=PLL output;
OPCLKDIV=0100
33
66
%
Input de-bounced
221 / fSYSCLK
222 / fSYSCLK
s
Input de-bounced
TOCLKSEL=1
219 / fSYSCLK
220 / fSYSCLK
s
Interrupt response time for accessory /
button detect
Input not de-bounced
0
s



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