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WM8953ECS/RV Scheda tecnica(PDF) 19 Page - Wolfson Microelectronics plc |
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WM8953ECS/RV Scheda tecnica(HTML) 19 Page - Wolfson Microelectronics plc |
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19 / 100 page ![]() Production Data WM8953 w PD, January 2009, Rev 4.0 19 AUDIO INTERFACE TIMING – TDM MODE In TDM mode, it is important that two ADC devices to not attempt to drive the ADCDAT pin simultaneously. The timing of the WM8953 ADCDAT tri-stating at the start and end of the data transmission is described in Figure 5 and the table below. Figure 5 Digital Audio Data Timing - TDM Mode Test Conditions AVDD=3.3V, DGND=AGND=0V, TA=+25 oC, Master Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER CONDITIONS MIN TYP MAX UNIT Audio Data Timing Information DCVDD = DBVDD = 3.6V 5 ns ADCDAT setup time from BCLK falling edge DCVDD = DBVDD = 1.71V 15 ns DCVDD = DBVDD = 3.6V 5 ns ADCDAT release time from BCLK falling edge DCVDD = DBVDD = 1.71V 15 ns |
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