IMX53IEC datasheet(32/173 Pages) FREESCALE

32 / 173 page

i.MX53 Applications Processors for Industrial Products, Rev. 6

Freescale Semiconductor

Electrical Characteristics

4.3.5

LVDS I/O DC Parameters

The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A,

“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.

Table 16 shows the Low Voltage Differential Signaling (LVDS) DC electrical characteristics. The

parameters in Table 16 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

4.4

Output Buffer Impedance Characteristics

This section defines the I/O Impedance parameters of the i.MX53 processor for the following I/O types:

•

General Purpose I/O (GPIO)

•

Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2, and DDR3 modes

•

Ultra High Voltage I/O (UHVIO)

•

LVDS I/O

NOTE

Output driver impedance is measured with “long” transmission line of

impedance Ztl attached to I/O pad and incident wave launched into

transmission lime. Rpu/Rpd and Ztl form a voltage divider that defines

specific voltage of incident wave relative to OVDD. Output driver

impedance is calculated from this voltage divider (see Figure 4).

Table 16. LVDS DC Electrical Characteristics

DC Electrical Characteristics

Symbol

Test Conditions

Min

Typ

Max

Unit

Output Differential Voltage

VOD

Rload = 100

Ω between

padP and padN

250

350

450

Output High Voltage

VOH

1.25

1.375

1.6

Output Low Voltage

VOL

0.9

1.025

1.25

Offset Voltage

VOS

1.125

1.2

1.375

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