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IMX53IEC Scheda tecnica(PDF) 52 Page - Freescale Semiconductor, Inc |
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IMX53IEC Scheda tecnica(HTML) 52 Page - Freescale Semiconductor, Inc |
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52 / 173 page  i.MX53 Applications Processors for Industrial Products, Rev. 6 52 Freescale Semiconductor Electrical Characteristics 4.6.6.3 General EIM Timing-Synchronous Mode Figure 16, Figure 17, and Table 38 specify the timings related to the EIM module. All EIM output control signals may be asserted and deasserted by an internal clock synchronized to the BCLK rising edge according to corresponding assertion/negation control fields. , Figure 16. EIM Outputs Timing Diagram Figure 17. EIM Inputs Timing Diagram Table 38. EIM Bus Timing Parameters 1 ID Parameter BCD = 0 BCD = 1 BCD = 2 BCD = 3 Min Max Min Max Min Max Min Max WE1 BCLK Cycle time2 t 2 x t 3 x t 4 x t WE2 BCLK Low Level Width 0.4 x t 0.8 x t 1.2 x t 1.6 x t WE4 Address CSx_B WE_B OE_B BCLK BEy_B ADV_B Output Data ... WE5 WE6 WE7 WE8 WE9 WE10 WE11 WE12 WE13 WE14 WE15 WE16 WE17 WE3 WE2 WE1 Input Data WAIT_B BCLK WE19 WE18 WE21 WE20 |
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