IMX53IEC datasheet(39/173 Pages) FREESCALE

39 / 173 page

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 6

Freescale Semiconductor

Table 23 shows the AC parameters for LPDDR2 I/O operating in LPDDR2 mode.

Table 24 shows the AC parameters for LPDDR2 I/O operating in DDR3 mode.

2 Vid(ac) specifies the input differential voltage | Vtr - Vcp | required for switching, where Vtr is the “true” input signal and Vcp

is the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).

3 The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)

indicates the voltage at which differential input signal must cross.

4 The typical value of Vox(ac) is expected to be about 0.5 x OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac)

indicates the voltage at which differential output signal must cross.

Table 23. LPDDR2 I/O LPDDR2 mode AC Characteristics1

1 Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

AC input logic high

Vih(ac)

—

Vref + 0.22

—

OVDD

AC input logic low

Vil(ac)

—

Vref - 0.22

AC differential input high voltage2

2 Vid(ac) specifies the input differential voltage | Vtr - Vcp | required for switching, where Vtr is the “true” input signal and Vcp

is the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).

Vidh(ac)

—

0.44

—

AC differential input low voltage

Vidl(ac)

—

0.44

Input AC differential cross point voltage3

3 The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)

indicates the voltage at which differential input signal must cross.

Vix(ac)

Relative to OVDD/2

-0.12

—

0.12

Over/undershoot peak

Vpeak

—

0.35

Over/undershoot area (above OVDD

or below OVSS)

Varea

266 MHz

—

0.6

V-ns

Single output slew rate

tsr

Ω to Vref. 5pF load.

Drive impedance= 40

Ω ± 30%

1.5

—

3.5

V/ns

Ω to Vref. 5 pF

load. Drive

impedance= 60

Ω ±

30%

1—

2.5

Skew between pad rise/fall asymmetry +

skew caused by SSN

tSKD

clk = 266 MHz

clk = 400 MHz

——

0.2

0.1

Table 24. LPDDR2 I/O DDR3 mode AC Characteristics1

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

AC input logic high

Vih(ac)

—

Vref + 0.175

—

OVDD

AC input logic low

Vil(ac)

—

Vref - 0.175

AC differential input voltage2

Vid(ac)

—

0.35

—

Input AC differential cross point voltage3

Vix(ac)

—

Vref - 0.15

—

Vref + 0.15

Output AC differential cross point voltage4

Vox(ac)

—

Vref - 0.15

—

Vref + 0.15

IMX53IEC Scheda tecnica(PDF) 39 Page - Freescale Semiconductor, Inc

IMX53IEC Scheda tecnica(HTML) 39 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL