IMX53IEC datasheet(35/173 Pages) FREESCALE

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Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 6

Freescale Semiconductor

Table 18 shows DDR output driver average impedance of the i.MX53 processor.

Table 18. DDR Output Driver Average Impedance1

1 Output driver impedance is controlled across PVTs (process, voltages, and temperatures) using calibration procedure and

pu_*cal, pd_*cal input pins.

Parameter

Symbol

Test Conditions

Drive strength (DSE)

Unit

000

001

010

011

100

101

110

111

Output

Driver

Impedance

Rdrv2

2 Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.

LPDDR1/DDR2 mode

NVCC_DRAM = 1.8 V

DDR_SEL = 00

Calibration resistance = 300

Ω3

3 Calibration is done against external reference resistor. Value of the resistor should be varied depending on DDR mode and

DDR_SEL setting.

Hi-Z

300

150

100

DDR2 mode

NVCC_DRAM = 1.8 V

DDR_SEL = 01

Calibration resistance = 180

Ω3

Hi-Z

180

DDR2 mode

NVCC_DRAM = 1.8 V

DDR_SEL = 10

Calibration resistance = 200

Ω3

Hi-Z

200

100

DDR2 mode

NVCC_DRAM= 1.8 V

DDR_SEL = 11

Calibration resistance = 140

Ω3

Hi-Z

140

LPDDR2 mode

NVCC_DRAM= 1.2 V

DDR_SEL = 014

Calibration resistance = 160

Ω3

4 If DDR_SEL = ‘01’ or DDR_SEL = ‘11’ are selected with NVCC_DRAM = 1.2 V for LPDDR2 operation, the external reference

resistor value must be 160

Ω for a correct ZQ calibration. In any case, reference resistors attached to the DDR memory

devices should be kept to 240

Ω per the JEDEC standard.

Hi-Z

160

LPDDR2 mode

NVCC_DRAM = 1.2 V

DDR_SEL = 10

Calibration resistance = 240

Ω3

Hi-Z

240

120

LPDDR2 mode

NVCC_DRAM = 1.2 V

DDR_SEL = 114

Calibration resistance = 160

Ω3

Hi-Z

160

DDR3 mode

NVCC_DRAM = 1.5 V

DDR_SEL = 00

Calibration resistance = 200

Ω3

Hi-Z

240

120

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