IMX53IEC datasheet(68/173 Pages) FREESCALE

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i.MX53 Applications Processors for Industrial Products, Rev. 6

Freescale Semiconductor

Electrical Characteristics

4.7.3

Enhanced Serial Audio Interface (ESAI) Timing Parameters

The ESAI consists of independent transmitter and receiver sections, each section with its own clock

generator. Table 48 shows the interface timing values. The number field in the table refers to timing signals

found in Figure 34 and Figure 35.

Table 48. Enhanced Serial Audio Interface (ESAI) Timing

No.

Characteristics1’2,3

Symbol

Expression3

Min

Max

Condition4 Unit

Clock cycle5

tSSICC

× Tc

30.0

—

i ck

Clock high period

• For internal clock

—2

× Tc − 9.0

—

• For external clock

—

× Tc

—

Clock low period

• For internal clock

—2

× Tc − 9.0

—

• For external clock

—

× Tc

—

SCKR rising edge to FSR out (bl) high

—

17.0

7.0

x ck

i ck a

SCKR rising edge to FSR out (bl) low

—

17.0

7.0

x ck

i ck a

SCKR rising edge to FSR out (wr) high6

—

19.0

9.0

x ck

i ck a

SCKR rising edge to FSR out (wr) low6

—

19.0

9.0

x ck

i ck a

SCKR rising edge to FSR out (wl) high

—

16.0

6.0

x ck

i ck a

SCKR rising edge to FSR out (wl) low

—

17.0

7.0

x ck

i ck a

Data in setup time before SCKR (SCK in synchronous

mode) falling edge

—

12.0

19.0

—

x ck

i ck

Data in hold time after SCKR falling edge

—

3.5

9.0

—

x ck

i ck

FSR input (bl, wr) high before SCKR falling edge6

—

2.0

12.0

—

x ck

i ck a

FSR input (wl) high before SCKR falling edge

—

2.0

12.0

—

x ck

i ck a

FSR input hold time after SCKR falling edge

—

2.5

8.5

—

x ck

i ck a

SCKT rising edge to FST out (bl) high

—

18.0

8.0

x ck

i ck

SCKT rising edge to FST out (bl) low

—

20.0

10.0

x ck

i ck

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