IMX53IEC datasheet(85/173 Pages) FREESCALE

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Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 6

Freescale Semiconductor

DISPx_DAT22

DAT[22]

—

R[6]

—

DISPx_DAT23

DAT[23]

—

R[7]

—

DIx_DISP_CLK

PixCLK

—

DIx_PIN1

—

VSYNC_IN May be required for anti-tearing

DIx_PIN2

HSYNC

—

DIx_PIN3

VSYNC

—

VSYNC out

DIx_PIN4

—

Additional frame/row synchronous

signals with programmable timing

DIx_PIN5

—

DIx_PIN6

—

DIx_PIN7

—

DIx_PIN8

—

DIx_D0_CS

—

CS0

—

DIx_D1_CS

—

CS1

Alternate mode of PWM output for

contrast or brightness control

DIx_PIN11

—

DIx_PIN12

—

DIx_PIN13

—

RS1

DIx_PIN14

—

RS2

Optional RS2

DIx_PIN15

DRDY/DV

DRDY

Data validation/blank, data enable

DIx_PIN16

—

Additional data synchronous

signals with programmable

features/timing

DIx_PIN17

—

Signal mapping (both data and control/synchronization) is flexible. The table provides examples.

2 This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line

start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data

during blanking intervals is not supported.

Table 59. Video Signal Cross-Reference (continued)

i.MX53

LCD

Comment1

Port Name

(x=0, 1)

RGB,

Signal

Name

(General)

RGB/TV Signal Allocation (Example)

Smart

16-bit

RGB

18-bit

RGB

24 Bit

RGB

8-bit

YCrCb2

16-bit

YCrCb

20-bit

YCrCb

Signal

Name

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