IMX53IEC datasheet(13/173 Pages) FREESCALE

13 / 173 page

Modules List

i.MX53 Applications Processors for Industrial Products, Rev. 6

Freescale Semiconductor

SECRAM

Secure /

Non-secure RAM

Internal

Memory

Secure / non-secure Internal RAM, controlled by SCC.

SJC

Secure JTAG

Interface

System

Control

Peripherals

JTAG manipulation is a known hacker’s method of executing unauthorized

program code, getting control over secure applications, and running code in

privileged modes. The JTAG port provides a debug access to several

hardware blocks including the ARM processor and the system bus.

The JTAG port must be accessible during platform initial laboratory bring-up,

manufacturing tests and troubleshooting, as well as for software debugging

by authorized entities. However, in order to properly secure the system,

unauthorized JTAG usage should be strictly forbidden.

In order to prevent JTAG manipulation while allowing access for

manufacturing tests and software debugging, the i.MX53 processor

incorporates a mechanism for regulating JTAG access. SJC provides four

different JTAG security modes that can be selected through an e-fuse

configuration.

SPBA

Shared

Peripheral Bus

Arbiter

System

Control

Peripherals

SPBA (shared peripheral bus arbiter) is a two-to-one IP bus interface (IP

bus) arbiter.

SPDIF

Sony Philips

Digital Interface

Multimedia

Peripherals

A standard digital audio transmission protocol developed jointly by the Sony

and Philips corporations. Both transmitter and receiver functionalists are

supported.

SRTC

Secure Real

Time Clock

Security

The SRTC incorporates a special system state retention register (SSRR)

that stores system parameters during system shutdown modes. This

NVCC_SRTC_POW. The NVCC_SRTC_POW can be energized separately

even if all other supply rails are shut down. This register is helpful for storing

warm boot parameters. The SSRR also stores the system security state. In

case of a security violation, the SSRR mark the event (security violation

indication).

SSI-1

SSI-2

SSI-3

I2S/SSI/AC97

Interface

Connectivity

Peripherals

The SSI is a full-duplex synchronous interface used on the i.MX53A

processor to provide connectivity with off-chip audio peripherals. The SSI

interfaces connect internally to the AUDMUX for mapping to external ports.

The SSI supports a wide variety of protocols (SSI normal, SSI network, I2S,

and AC-97), bit depths (up to 24 bits per word), and clock/frame sync

options.

Each SSI has two pairs of 8 x 24 FIFOs and hardware support for an

external DMA controller in order to minimize its impact on system

performance. The second pair of FIFOs provides hardware interleaving of a

second audio stream, which reduces CPU overhead in use cases where two

time slots are being used simultaneously.

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

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