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CDPCLK4 Scheda tecnica(PDF) 130 Page - Altera Corporation

Il numero della parte CDPCLK4
Spiegazioni elettronici  Cyclone III Device Handbook
PDF  274 Pages
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Produttore elettronici  ALTERA [Altera Corporation]
Homepage  http://www.altera.com
Logo ALTERA - Altera Corporation

CDPCLK4 Scheda tecnica(HTML) 130 Page - Altera Corporation

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Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Standards Support
Cyclone III Device Handbook
December 2011
Altera Corporation
Volume 1
Designing with LVDS
Cyclone III device family I/O banks support LVDS I/O standard. The left and right
I/O banks support true LVDS transmitters. On the top and bottom I/O banks, the
emulated LVDS transmitters are supported using two single-ended output buffers
with external resistors. One of the single-ended output buffers is programmed to have
opposite polarity. The LVDS receiver requires an external 100- termination resistor
between the two signals at the input buffer.
Figure 7–2 shows a point-to-point LVDS interface using Cyclone III device family true
LVDS output and input buffers.
Figure 7–3 shows a point-to-point LVDS interface with Cyclone III device family
LVDS using two single-ended output buffers and external resistors.
BLVDS I/O Standard Support in the Cyclone III Device Family
The BLVDS I/O standard is a high-speed differential data transmission technology
that extends the benefits of standard point-to-point LVDS to multipoint configuration
that supports bidirectional half-duplex communication. BLVDS differs from standard
LVDS by providing a higher drive to achieve similar signal swings at the receiver
while loaded with two terminations at both ends of the bus.
Figure 7–2. Cyclone III Device Family LVDS Interface with True Output Buffer on the Left and Right I/O Banks
Transmitting Device
Cyclone III Device Family
100
Ω
Cyclone III
Device
Family Logic
Array
100
Ω
Input Buffer
Output Buffer
Receiving Device
txout +
txout -
rxin +
rxin -
txout +
txout -
rxin +
rxin -
50
Ω
50
Ω
50
Ω
50
Ω
Figure 7–3. LVDS Interface with External Resistor Network on the Top and Bottom I/O Banks (1)
Note to Figure 7–3:
(1) R
S = 120  ; RP =170 
LVDS Receiver
100
Ω
50
Ω
Cyclone III Device Family
Resistor Network
Emulated
LVDS Transmitter
RS
RP
RS
50
Ω



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