CDPCLK4 datasheet(134/274 Pages) ALTERA

134 / 274 page

7–12

Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family

High-Speed I/O Standards Support

Cyclone III Device Handbook

December 2011

Altera Corporation

Volume 1

Figure 7–7 shows the RSDS interface with a single resistor network on the top and

bottom I/O banks.

LVPECL I/O Support in the Cyclone III Device Family

The LVPECL I/O standard is a differential interface standard that requires a 2.5-V

VCCIO. This standard is used in applications involving video graphics,

telecommunications, data communications, and clock distribution. The Cyclone III

device family supports the LVPECL input standard at the dedicated clock input pins

only. The LVPECL receiver requires an external 100- termination resistor between

the two signals at the input buffer.

f For more information about the LVPECL I/O standard electrical specification, refer to

the Cyclone III Device Data Sheet and Cyclone III LS Device Data Sheet chapters.

AC coupling is required when the LVPECL common mode voltage of the output

buffer is higher than the Cyclone III device family LVPECL input common mode

voltage.

Figure 7–8 shows the AC-coupled termination scheme. The 50- resistors used at the

receiver are external to the device. DC-coupled LVPECL is supported if the LVPECL

output common mode voltage is in the Cyclone III device family LVPECL input buffer

specification (Figure 7–9).

Figure 7–7. RSDS Interface with Single Resistor Network on the Top and Bottom I/O Banks

Note to Figure 7–7:

(1) R

P = 100 

RSDS Receiver

100

Cyclone III Device Family

Single Resistor Network

Emulated

RSDS Transmitter

Figure 7–8. LVPECL AC-Coupled Termination

Cyclone III Device Family

LVPECL Receiver



VICM

Z0 = 50 

LVPECL

Transmitter

0.1 µF

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