CDPCLK4 datasheet(195/274 Pages) ALTERA

195 / 274 page

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family

9–37

Configuration Features

August 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

In a multi-device PS configuration, the nCE pin of the first device is connected to GND

while its nCEO pin is connected to the nCE pin of the next device in the chain. The nCE

input of the last device comes from the previous device, while its nCEO pin is left

floating. After the first device completes configuration in a multi-device configuration

chain, its nCEO pin drives low to activate the nCE pin of the second device, which

prompts the second device to begin configuration. The second device in the chain

begins configuration in one clock cycle. Therefore, the transfer of data destinations is

transparent to the external host device. All other configuration pins (nCONFIG,

nSTATUS

, DCLK, DATA[0], and CONF_DONE) are connected to every device in the chain.

Configuration signals can require buffering to ensure signal integrity and prevent

clock skew problems. Ensure that the DCLK and DATA lines are buffered. Because all

device CONF_DONE pins are tied together, all devices initialize and enter user mode at

the same time.

If any device detects an error, configuration stops for the entire chain and the entire

chain must be reconfigured because all nSTATUS and CONF_DONE pins are tied together.

For example, if the first device flags an error on nSTATUS, it resets the chain by pulling

its nSTATUS pin low. This behavior is similar to a single device detecting an error.

You can have multiple devices that contain the same configuration data in your

system. To support this configuration scheme, all device nCE inputs are tied to GND,

while the nCEO pins are left floating. All other configuration pins (nCONFIG, nSTATUS,

DCLK

, DATA[0], and CONF_DONE) are connected to every device in the chain.

Configuration signals can require buffering to ensure signal integrity and prevent

clock skew problems. Ensure that the DCLK and DATA lines are buffered. Devices must

be of the same density and package. All devices start and complete configuration at

the same time.

CDPCLK4 Scheda tecnica(PDF) 195 Page - Altera Corporation