CDPCLK4 datasheet(191/274 Pages) ALTERA

191 / 274 page

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family

9–33

Configuration Features

August 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

Programming Parallel Flash Memories

Supported parallel flash memories are external non-volatile configuration devices.

They are industry standard microprocessor flash memories. For more information

about the supported families for the commodity parallel flash, refer to Table 9–11 on

page 9–24.

Cyclone III devices in a single- or multiple-device chains support in-system parallel

flash programming with the JTAG interface using the flash loader megafunction. For

Cyclone III devices, the board-intelligent host or download cable uses four JTAG pins

to program the parallel flash in system, even if the host or download cable cannot

access the configuration pins of the parallel flash.

f For more information about using the JTAG pins on Cyclone III devices to program

the parallel flash in-system, refer to AN 478: Using FPGA-Based Parallel Flash Loader

(PFL) with the Quartus II Software.

In the AP configuration scheme, the default configuration boot address is 0×010000

when represented in 16-bit word addressing in the supported parallel flash memory

(Figure 9–13). In the Quartus II software, the default configuration boot address is

0x020000 because it is represented in 8-bit byte addressing. Cyclone III devices

configure from word address 0x010000, which is equivalent to byte address 0x020000.

1 The Quartus II software uses byte addressing for the default configuration boot

address. You must set the start address field to 0x020000.

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