CDPCLK4 datasheet(203/274 Pages) ALTERA

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Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family

9–45

Configuration Features

August 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

Figure 9–21 shows how to configure multiple devices using a MAX II device. This

circuit is similar to the FPP configuration circuit for a single device, except the

Cyclone III device family is cascaded for a multi-device configuration.

In a multi-device FPP configuration, the nCE pin of the first device is connected to

GND while its nCEO pin is connected to the nCE pin of the next device in the chain. The

nCE

input of the last device comes from the previous device while its nCEO pin is left

floating. After the first device completes configuration in a multi-device configuration

chain, its nCEO pin drives low to activate the nCE pin of the second device, which

prompts the second device to begin configuration. The second device in the chain

begins configuration in one clock cycle; therefore, the transfer of data destinations is

transparent to the MAX II device. All other configuration pins (nCONFIG, nSTATUS,

DCLK

, DATA[7..0], and CONF_DONE) are connected to every device in the chain. The

configuration signals may require buffering to ensure signal integrity and prevent

clock skew problems. Ensure that the DCLK and DATA lines are buffered. All devices

initialize and enter user mode at the same time because all device CONF_DONE pins are

tied together.

All nSTATUS and CONF_DONE pins are tied together and if any device detects an error,

configuration stops for the entire chain and the entire chain must be reconfigured. For

example, if the first device flags an error on nSTATUS, it resets the chain by pulling its

nSTATUS

pin low. This behavior is similar to a single device detecting an error.

Figure 9–21. Multi-Device FPP Configuration Using an External Host

Notes to Figure 9–21:

(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the

chain. VCC must be high enough to meet the VIH specification of the I/O on the device and the external host.

(2) Connect the pull-up resistor to the VCCIO supply voltage of the I/O bank in which the nCE pin resides.

(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.

(4) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0],

refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to VCCA or ground.

(5) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[7..0] and DCLK must fit the maximum overshoot

equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.

External Host

(MAX II Device or

Microprocessor)

Memory

ADDR

Cyclone III Device Family 1

nSTATUS

CONF_DONE

10 k



nCE

nCEO

DATA[7..0]

GND

VCCIO (1) VCCIO (1)

10 k



MSEL[3..0]

DATA[7..0] (5)

nCONFIG

DCLK (5)

nSTATUS

CONF_DONE

nCE

nCEO

MSEL[3..0]

N.C. (3)

DATA[7..0] (5)

nCONFIG

DCLK (5)

VCCIO (2)

10 k



Cyclone III Device Family 2

(4)

Buffers (5)

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