P83C266BDR datasheet(38/92 Pages) PHILIPS

38 / 92 page

1999 Mar 10

Philips Semiconductors

Product speciﬁcation

Microcontrollers for PAL/SECAM TV

with OSD and VST

P8xCx66 family

15.2

14-bit PWM output (TPWM)

The on-chip 14-bit DAC has one output with a resolution of

16384 levels for Voltage Synthesized Tuning (VST).

The output is active HIGH, the HIGH period being

determined by the values stored in the SFRs TDACH and

TDACL. The 14-bit DAC output is connected to the TPWM

pin.

TPWM shares the same pin as port line P5.0. Selection of

the pin function as either a PWM output or as a port line is

achieved using the TPWME bit in SFR TDACH, see

Section 15.2.5.

The block diagram for the 14-bit PWM circuit is shown in

Fig.22 and consists of:

• Two 7-bit SFRs: TDACH and TDACL

• One 14-bit register TDACREG

• One coarse control block for the generation of the

coarse adjustment pulse

• One fine control block for the generation of the fine

adjustment pulses

• One 14-bit counter running at fTDAC

• One mixer block that combines the coarse adjustment

pulse and fine tuning pulses; the resultant pulse pattern

is fed to the TPWM output.

Data is loaded into the 14-bit data latch (TDACREG) from

the two 7-bit data latches (TDACL and TDACH) at the

beginning of the first Tsub period, after TDACH has been

written to. To ensure that correct data is loaded into

TDACREG, the data held in TDACL must be valid before

the write operation to TDACH is started. In other words,

TDACL must be written first before TDACH can be written

to. Examples of valid and invalid loading sequences are

shown in Fig.23.

Once TDACREG has been loaded it takes one Tsub period

to generate the appropriate pulse patterns. To ensure

correct operation of the DAC, two Tsub periods should be

allowed before any further changes to the data latches are

made.

The upper seven bits of TDACREG, identified as VSTH,

are used for coarse adjustment and the lower seven bits,

identified as VSTL, are used for fine adjustment.

The outputs OUT1 and OUT2 of the coarse and fine pulse

controllers are ‘ORed’ in the mixer to give the TPWM

output.

The 14-bit counter is continuously running and is clocked

by fTDAC which is 1⁄4fosc.

Figure 24 shows the output of the coarse pulse controller

when VSTH = 001 1101; Fig.25 shows the output of the

fine pulse controller when VSTL = 1111010, and Fig.26

shows a typical TPWM output after the ‘OR’ operation has

been carried out by the mixer.

15.2.1

REPETITION TIME OF OUT1 AND OUT2:

The repetition period of OUT1 (Tsub) may be calculated as

shown in Equation (1).

(1)

Where

The repetition period of OUT2 (Tstd) may be calculated as

shown in Equation (2).

(2)

15.2.2

COARSE ADJUSTMENT

An active HIGH pulse is generated in every subperiod

(except the first one); the pulse duration being determined

by the contents of VSTH. The coarse pulses are generated

at the OUT1 output. The coarse pulse output is LOW at the

start of each subperiod and will remain LOW until the time

has elapsed. The output will then go

HIGH and remain HIGH until the start of the next

subperiod. The coarse pulse duration is

The trailing edge of each coarse pulse coincides with the

end of each Tsub period. If VSTH = 0000000, then the

coarse output is LOW for the complete period. If the

contents of VSTH = 1111111, then the coarse output is

LOW for the first t0 period but will go HIGH for the

remaining 127

× t0 periods of Tsub.

15.2.3

FINE ADJUSTMENT

Fine adjustment is achieved by generating an additional

pulse in specific subperiods. These additional pulses

appear at the OUT2 output. The pulse is added at the start

of the selected subperiod and has a pulse width of t0.

The value held in VSTL determines the subperiod in which

an additional pulse is generated and also determines the

number of additional pulses that will be added during one

Tstd period. Table 39 shows the relationship between the

value held in VSTL, the subperiod during which an

additional pulse OUT2 is generated and the total number

of additional OUT2 pulses generated.

sub

128

TDAC

--------------

128

TDAC

--------------

std

128

TDAC

---------------

128

16384

128

VSTH

–

() t

[]

VSTH

()

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