P83C266BDR datasheet(18/92 Pages) PHILIPS

18 / 92 page

1999 Mar 10

Philips Semiconductors

Product speciﬁcation

Microcontrollers for PAL/SECAM TV

with OSD and VST

P8xCx66 family

10.3

Serial Control Register (S1CON)

Table 6

Serial Control Register (SFR address D8H)

Table 7

Description of S1CON bits

76543210

CR2

ENS1

STA

STO

CR1

CR0

BIT

SYMBOL

DESCRIPTION

ENSI

Enable Serial I/O. When ENSI = 0, the SIO is disabled and reset. The SDA and SCL

outputs are in a high-impedance state; P1.5 and P1.6 function as open-drain ports.

When ENSI = 1, the SIO is enabled. The P1.5 and P1.6 port latches must be set to

logic 1.

STA

START ﬂag. When the STA bit is set in Slave mode, the SIO hardware checks the

status of the I2C-bus and generates a START condition if the bus is free. If STA is set

while the SIO is in Master mode, SIO transmits a repeated START condition.

4STO

STOP ﬂag. With this bit set while in Master mode a STOP condition is generated. When

a STOP condition is detected on the bus, the SIO hardware clears the STO ﬂag. In the

Slave mode, the STO ﬂag may also be set to recover from an error condition. In this

case, no STOP condition is transmitted to the I2C-bus interface. However, the SIO

hardware behaves as if a STOP condition has been received and releases SDA and

SCL. The SIO then switches to the ‘not addressed’ slave receiver mode. The STO ﬂag

is automatically cleared by hardware.

3SI

SIO interrupt ﬂag. When the SI ﬂag is set, an acknowledge is returned after any one of

the following conditions:

• A START condition is generated in Master mode

• Own slave address received during AA = 1

• General call address received while S1ADR.0 = 1 and AA = 1

• Data byte received or transmitted in Master mode (even if arbitration is lost)

• Data byte received or transmitted as selected slave

• STOP or START condition received as selected slave receiver or transmitter.

2AA

Assert Acknowledge. When the AA ﬂag is set, an acknowledge (LOW level to SDA)

will be returned during the acknowledge clock pulse on the SCL line when:

• Own slave address is received

• General call address is received (S1ADR.0 = 1)

• Data byte received while device is programmed as a Master receiver

• Data byte received while device is a selected Slave receiver.

With AA = 0, no acknowledge will be returned. Consequently, no interrupt is requested

when the ‘own slave address’ or general call address is received.

CR2

Clock Rate selection. These three bits determine the serial clock frequency when SIO

is in a Master mode; see Table 8. The maximum I2C-bus frequency is 400 KHz.

CR1

CR0

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