P83C266BDR datasheet(22/92 Pages) PHILIPS

22 / 92 page

1999 Mar 10

Philips Semiconductors

Product speciﬁcation

Microcontrollers for PAL/SECAM TV

with OSD and VST

P8xCx66 family

11 INTERRUPT SYSTEM

External events and the real-time driven on-chip

peripherals require service by the CPU asynchronous to

the execution of any particular section of code. To tie the

asynchronous activities of these functions to normal

program execution a multiple-source, two-priority-level,

nested interrupt system is provided. The P8xCx66

acknowledges interrupt requests from twelve sources as

shown in Table 20.

Each interrupt vectors to a separate location in program

memory for its service routine. Each source can be

individually enabled or disabled by using corresponding

bits in the Interrupt Enable Registers (IEN0 and IEN1).

The priority level is selected via the Interrupt Priority

Registers (IP0 and IP1). All enabled sources can be

globally disabled or enabled. The minimum width of the

external interrupt signal is

≥6 XTAL clocks. The maximum

width of the interrupt signal is the total length of all

instructions in the interrupt service routine until the clear

instruction of the IRQ bit. The external interrupts are INT0,

INT1, P1.0, P1.1, P1.2, P1.3, P1.4 and P1.7.

11.1

External interrupts INT2 to INT7 and INT9

Port 1 lines also serve as additional interrupts

INT2 to INT7 (P1.0, P1.1, P1.2, P1.3, P1.4 and P1.7).

INT7 is used by the derivative functional blocks as follows:

VSYNC interrupt 0063H

Using the IX1 register, each pin may be initialized to be

either active HIGH or active LOW except INT7 which is

fixed active HIGH because this interrupt is from another

derivative function. IRQ1 is the Interrupt Request Flag

must be cleared by software, i.e. via the interrupt software.

11.2

Interrupt priority

Each interrupt source can be set to either high or low

priority. If both priorities are requested simultaneously, the

controller will branch to the high priority vector.

A low priority interrupt can only be interrupted by a high

priority interrupt. A high priority interrupt routine cannot be

interrupted

11.3

Related registers

The following registers are used in conjunction with the

interrupt system.

Table 19 Interrupt registers

ADDRESS

Interrupt Polarity Register (IX1)

E9H

Interrupt Request Flag Register (IRQ1)

C0H

Interrupt Enable Register 0 (IEN0)

A8H

Interrupt Enable Register 1 (IEN1);

interrupts INT2 to INT9

E8H

Interrupt Priority Register 0 (IP0)

B8H

Interrupt Priority Register 1 (IP1);

interrupts INT2 to INT9

F8H

Table 20 Interrupt request (priority within level)

INTERRUPT MNEMONIC

SOURCE

VECTOR ADDRESS

PX0 (highest)

external interrupt 0 (INT0)

0003H

I2C-bus

002BH

Timer 0 overflow

000BH

PX2

P1.0 port line

0033H

PX6

P1.4 port line

005BH

PX1

external interrupt 1 (INT1)

0013H

PX3

P1.1 port line

003BH

PX7

VSYNC interrupt

0063H

Timer 1 overflow

001BH

PX4

P1.2 port line

0043H

PX5

P1.3 port line

004BH

PX9 (lowest)

P1.7 port line

0073H

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