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P83C266BDR Scheda tecnica(PDF) 46 Page - NXP Semiconductors

Il numero della parte P83C266BDR
Spiegazioni elettronici  80C51 8-bit CPU
PDF  92 Pages
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Produttore elettronici  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

P83C266BDR Scheda tecnica(HTML) 46 Page - NXP Semiconductors

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1999 Mar 10
46
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
17 ON-SCREEN DISPLAY (OSD)
17.1
Features
• Programmable active level polarity of VSYNC, HSYNC
and digital RGB with polarity selection
• Display RAM: 192 × 12 bits
• Display character fonts: 128 (126 customer fonts plus
2 reserved codes)
• One programmable vertical starting position counter
giving 63 different vertical starting positions
• One programmable horizontal starting position counter
giving 110 different horizontal starting positions
• Character size: 4 character sizes on a line-by-line basis
• Character matrix: 12 × 18 with no spacing between
characters
• Foreground colours: 8 on a character-by-character
basis
• Background/shadowing modes: Two primary modes:
TV mode and Frame mode on a frame basis. Each
primary mode has four sub-modes on a character row
basis:
– Sub-mode 1: Superimpose (no background)
– Sub-mode 2: North-West shadowing
– Sub-mode 3: Box background
– Sub-mode 4: Border shadowing.
• Background colours: 8 on a word-by-word basis.
Available when background is either in North-West
shadowing, Box background, Border shadowing and
Frame shadowing sub-modes.
• Display RAM starting address is programmable. Fast
switching between banks of display characters is
possible through software control.
• HSYNC driven PLL (frequency determined by SFR
OSPLL)
• Character blinking ratio: 1 : 1
• Character blinking frequency: programmable using
fVSYNC divisors of 32 and 64, on a character basis
• Display format: Flexible display format by using CR
(carriage return) and SP1, SP2 (space) and split space
code
• Display RAM address post increment each time new
data is written
• Vertical jitter cancelling circuit to avoid unstable VSYNC
leading edge mismatch with HSYNC signal
• OSD clock operating frequency: 4 to 12 MHz
• Meshing function.
17.2
Flexible display format
Figures 28 and 29 show typical examples of on-screen
displays generated by the P8xCx66.
There are 128 different fonts available two of which, the
Carriage Return (CR) code and the Space (SP) code, are
reserved for special functions. The CR code performs the
same function as the return key on a conventional
keyboard, the display will start on the next line. The SP
code enables the background colour of the space itself
and that of the following characters to be changed.
There are 192 display RAM locations (00H to BFH) and
these are considered as a linear addressed RAM. The first
character fetched is from the display RAM address pointed
to by the contents of the Special Function Register
OSSTART (see Section 17.3.5).
The OSD starting position is programmable, this is
described in detail in Section 17.2.1.
Two other registers are used to program the OSD:
OSCON and OSCON2. These registers are described in
Sections 17.3.2 and 17.3.6.
17.2.1
OSD STARTING POSITION
The horizontal and vertical starting position of the display
is controlled by two counters: SFRs OSORGH and
OSORGV.
OSORGH controls the horizontal starting position. This
counter is incremented every OSD clock cycle after the
falling edge of HSYNCP (after the polarity selection).
HSYNCP is always active HIGH. OSORGH is described in
Section 17.3.4.
OSORGV controls the vertical starting position. This
counter is incremented every HSYNC cycle and is reset by
the VSYNC signal. OSORGV is described in
Section 17.3.3.
The OSD starting position reference points are shown in
Fig.32.



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