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P83C266BDR Scheda tecnica(PDF) 83 Page - NXP Semiconductors |
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P83C266BDR Scheda tecnica(HTML) 83 Page - NXP Semiconductors |
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83 / 92 page ![]() This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... − 35 P2.4 I/O CMOS open-drain + Rpu(5) Yes −− − 36 P2.5 I/O CMOS open-drain + Rpu(5) Yes −− 22 37 B O − push-pull, 1.6 mA No note 6 LOW(7) SW con 23 38 G O − push-pull, 1.6 mA No note 6 LOW(7) SW con 24 39 R O − push-pull, 1.6 mA No note 6 LOW(7) SW con 25 40 FB O − push-pull, 1.6 mA No note 6 LOW(7) SW con 26 41 HSYNC I TTL STr −− − − SW con 27 42 VSYNC I TTL STr −− − − SW con − 43 n.c. −− − − − − − 44 n.c. −− − − − − 28 45 VDDA −− − − − − 29 46 VSS −− − − − − − 47 P2.6 I/O CMOS open-drain + Rpu(5) Yes −− 30 48 VPP I 12.75 V −− − − − 49 VSS −− − − − − 31 50 XTALIN I CPU XTAL −− − − 32 51 XTALOUT O CPU XTAL −− − − − 52 P2.7 I/O CMOS open-drain + Rpu(5) Yes −− − 53 IDLPDEM O − push-pull, 2 mA note 4 −− 33 54 RESET I CMOS STr + Rpd(8) −− − − − 55 EMUPBX O − push-pull, 2 mA note 4 −− − 56 VSS −− − − − − 34 − VSS − note 9 −− − − 34 57 P1.0 I/O TTL STr open-drain + Rpu(5) Yes original state Z(2) 34 57 VDD − notes 9 and 10 −− − − 35 58 P1.1 I/O TTL STr open-drain Yes original state Z(2) 35 58 INT1 I TTL STr −− − − 36 59 P1.2 I/O TTL STr open-drain Yes original state Z(2) 36 59 T0 I TTL STr −− − − − 60 n.c. −− − − − − PIN SYMBOL TYPE INPUT LEVEL OUTPUT TYPE SLOPE CONTROL OUTPUT IN IDLE MODE OUTPUT AFTER RESET ACTIVE STATE SW CONTROL SDIP42 PLCC68 |
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