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SSM4567ACBZ-R7 Scheda tecnica(PDF) 33 Page - Analog Devices |
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SSM4567ACBZ-R7 Scheda tecnica(HTML) 33 Page - Analog Devices |
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33 / 52 page ![]() Data Sheet SSM4567 Rev. 0| Page 33 of 52 REGISTER DETAILS POWER CONTROL REGISTER Address: 0x00, Reset: 0x81, Name: POWER_CTRL Table 26. Bit Descriptions for POWER_CTRL Bits Bit Name Settings Description Reset Access 7 APWDN_EN Auto Power-Down Enable. Auto power down automatically puts the IC in a low power state when 2048 consecutive zero input samples have been received. 0x1 R/W 0 Auto Power-Down Disabled. 1 Auto Power-Down Enabled When APWDN_EN=1. The device automatically powers down when 2048 consecutive zero value input samples have been received. The device automatically powers up when a single non zero sample is received. 6 BSNS_PWDN Battery Voltage Sense Power Down. 0x0 R/W 0 Battery Voltage Sense Powered On. 1 Battery Voltage Sense Powered Off. 5 VSNS_PWDN Voltage Sense Power-Down. 0x0 R/W 0 Voltage Sense Powered On. 1 Voltage Sense Powered Off. 4 ISNS_PWDN Current Sense Power Down. 0x0 R/W 0 Current Sense Powered On. 1 Current Sense Powered Off. 3 BOOST_PWDN Boost Converter Power-Down. When the boost converter is powered down, the Class-D operates directly from VBAT power supply. 0x0 R/W 0 Boost Converter Enabled. 1 Boost Converter Powered Down. 2 AMP_PWDN Amplifier Power-Down. 0x0 R/W 0 Amplifier and DAC Normal Operation. 1 Amplifier and DAC Powered Down. 1 VBAT_ONLY Class-D Power Switch. 0x0 R/W 0 Class-D can switch between VBAT and PVDD as a five-level output. 1 Class-D powered from VBAT only, even if the booster is on. 0 SPWDN Master Software Power-Down. Software power-down puts all blocks except the I2C interface in a low power state. 0x1 R/W 0 Normal Operation. 1 Software Master Power-Down. |
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