SSM4567ACBZ-R7 datasheet(50/52 Pages) AD

50 / 52 page

SSM4567

Data Sheet

Rev. 0| Page 50 of 52

Table 46. Bit Descriptions for MCLK_RATIO

Bits

Bit Name

Settings

Description

Reset

Access

[7:5]

RESERVED

Reserved.

0x0

R/W

AMCS

Auto MCS. Automatic or manual Master Clock ratio Setting

0x1

R/W

Manual MCLK ratio Setting by using the MCS Bits

Automatic MCLK ratio detection The Master Clock ratio Setting that is detected is stored

in the MCS register bits to allow the setting to be read.

[3:0]

MCS

MCLK Ratio Setting (when AMCS = 1, this reads back the auto detection setting )

0x1

R/W

0000

64 × fs

0001

128 × fs

0010

192 × fs

0011

256 × fs

0100

384 × fs

0101

512 × fs

0110

50 × fs

0111

100 × fs

1000

200 × fs

1001

400 × fs

BOOST CONTROL 1 REGISTER

Address: 0x15, Reset: 0x03, Name: BOOST_CTRL_1

Table 47. Bit Descriptions for BOOST_CTRL_1

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

ADJ_PGATE

PMOS driver speed setting

0x0

R/W

Fastest pmos driver speed

Fast pmos driver speed

Slow pmos driver speed

Slowest pmos driver speed

[5:3]

RESERVED

Reserved.

0x0

R/W

EN_DSCGB

Output discharge switch enable

0x0

R/W

Disable the output discharge switch

Enable the output discharge switch

FPWMB

Force PWM mode for the boost

0x1

R/W

Force PWM Mode

PWM mode + PSM mode

SEL_FREQ

Boost clock frequency Select

0x1

R/W

2.5 MHz

1.25 MHz

SSM4567ACBZ-R7 Scheda tecnica(PDF) 50 Page - Analog Devices

SSM4567ACBZ-R7 Scheda tecnica(HTML) 50 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Scheda tecnica Scarica

Link URL