SSM4567ACBZ-R7 datasheet(22/52 Pages) AD

22 / 52 page

SSM4567

Data Sheet

Rev. 0| Page 22 of 52

Figure 44. Limiter Example (LIM_EN = 0b01, VBAT_TRACK = 0)

I2C CONTROL

The SSM4567 supports a 2-wire, serial, I2C-compatible

microprocessor bus driving multiple peripherals. Two pins,

serial data (SDA) and serial clock (SCL), carry information

between the SSM4567 and the system I2C master controller. The

SSM4567 is always a slave on the bus, meaning it cannot initiate

a data transfer. Each slave device is recognized by a unique

address. The address byte format is shown in Table 14. The

address resides in the first seven bits of the I2C write. The LSB

of this byte sets either a read or write operation. Logic Level 1

corresponds to a read operation, and Logic Level 0 corresponds

to a write operation.

Both SDA and SCL need 2.2 kΩ pull-up resistors for proper

operation. Only one set of pull-up resistors are required for the

entire I2C bus. The voltage on these signal lines must not be

more than 3.3 V.

Table 14. I2C Chip Address Byte Format

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

I2C Addr.

MSB

I2C Addr.

LSB

R/W

Table 15. I2C Device Address Selection

Device Address

(7-Bit Format)

Device Address

(8-Bit Format)

LR_SEL/ADDR Pin

Configuration

0x34

0x68

Tied to AGND

0x35

0x6A

Tied to IOVDD

0x36

0x6C

Open

Addressing

Initially, each device on the I2C bus is in an idle state, monitoring

the SDA and SCL lines for a start condition and the proper

address. The I2C master initiates a data transfer by establishing a

start condition, defined by a high-to-low transition on SDA while

SCL remains high. This indicates that an address/data stream

follows. All devices on the bus respond to the start condition

and shift the next eight bits (the 7-bit address plus the R/W bit)

MSB first. The device that recognizes the transmitted address

responds by pulling the data line low during the ninth clock

pulse. The device address of the SSM4567 is determined by the

state of the LR_SEL/ADDR pin. When the LR_SEL/ADDR pin

is pulled to ground, the device address is 0x34.

This ninth bit is known as an acknowledge bit. All other devices

withdraw from the bus at this point and return to the idle

condition. The R/W bit determines the direction of the data. A

Logic 0 on the LSB of the first byte means the master writes

information to the peripheral, whereas a Logic 1 means the

master reads information from the peripheral after writing the

subaddress and repeating the start address. A data transfer takes

place until a stop condition is encountered. A stop condition

occurs when SDA transitions from low to high while SCL is

held high. The timing for the I2C port is shown in Figure 45.

Stop and start conditions can be detected at any stage during the

data transfer. If these conditions are asserted out of sequence with

normal read and write operations, the SSM4567 immediately

jumps to the idle condition. During a given SCL high period,

the user must issue only one start condition, one stop condition, or

a single stop condition followed by a single start condition. If an

invalid subaddress is issued by the user, the SSM4567 does not

issue an acknowledge and returns to the idle condition. If the

user exceeds the highest subaddress while in auto-increment mode,

one of two actions is taken. In read mode, the SSM4567 outputs

the highest subaddress register contents until the master device

issues a no acknowledge, indicating the end of a read. A no

acknowledge condition is where the SDA line is not pulled low

on the ninth clock pulse on SCL. If the highest subaddress location

is reached while in write mode, the data for the invalid byte is

not loaded into any subaddress register, a no acknowledge is

issued by the SSM4567, and the device returns to the idle

condition.

I2C Read and Write Operations

Figure 46 shows the format of a single-word write operation.

Every ninth clock, the SSM4567 issues an acknowledge message

by pulling SDA low.

Figure 47 shows the format of a burst mode write sequence.

This figure shows an example where the target destination

registers are two bytes. The SSM4567 knows to increment its

subaddress register every byte because the requested subaddress

corresponds to a register or memory area with a byte word length.

The timing of a single-word read operation is shown in Figure 48.

Note that the first R/W bit is 0, indicating a write operation.

This is because the subaddress still must be written to set up the

internal address. After the SSM4567 acknowledges the receipt

of the subaddress, the master must issue a repeated start

command, followed by the chip address byte with the R/W set

to 1 (read). This causes the SSM4567 SDA to reverse and begin

driving data back to the master. The master then responds every

ninth pulse with an acknowledge pulse to the SSM4567.

VBAT

LIM_EN = 01

VBAT_TRACK = 0

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