GD25S513MDFEG datasheet(16/94 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25S513MD

a new address and mode bits. This reduces the time needed to send each command when the same command type is

repeated in a sequence of commands.

Dummy cycles provide additional latency that is needed to complete the initial read access of the flash array before

data can be returned to the host system. Some read commands require additional latency cycles as the SCLK frequency is

increased.

The following latency code tables provide different latency settings that are configured by GigaDevice.

Table 11 Latency Code and DTR Mode Frequency Table

LC1, LC0

Dummy clock cycles

Quad IO DTR Read (MHz)

70/80R

Note:

The default value of latency code is 00.

Not 100% tested in production.

“R” means VCC range=3.0V~3.6V.

DRV1, DRV0 bits

The DRV1 and DRV0 bits are used to determine the output driver strength for the Read operations.

Table 10 Driver Strength for Read Operations

DRV1,DRV0

Driver Strength

100%

75% (Default)

Reserved

PE bit

The Program Error (PE) bit is a read only bit that indicates a program failure. It will also be set when the user attempts

to program a protected array sector or access the locked OTP space.

Error bits can be reset by CLEAR FLAG STATUS REGISTER command (30H).

EE bit

The Erase Error (EE) bit is a read only bit that indicates an erase failure. It will also be set when the user attempts to

erase a protected array sector or access the locked OTP space.

Error bits can be reset by CLEAR FLAG STATUS REGISTER command (30H).

ADS bit

The Address Status (ADS) bit is a read only bit that indicates the current address mode the device is operating in. The

device is in 3-Byte address mode when ADS=0 (default), and in 4-Byte address mode when ADS=1.

ADP bit

The Address Power-up (ADP) bit is a non-volatile writable bit that determines the initial address mode when the device

is powered on or reset. This bit is only used during the power on or device reset initialization period. When ADP=0 (factory

default), the device will power up into 3-Byte address mode, the Extended Address Register must be used to access memory

GD25S513MDFEG Scheda tecnica(PDF) 16 Page - GigaDevice Semiconductor (Beijing) Inc.