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GD25S513MDFEG Scheda tecnica(PDF) 37 Page - GigaDevice Semiconductor (Beijing) Inc.

Il numero della parte GD25S513MDFEG
Spiegazioni elettronici  3.3V Uniform Sector Dual and Quad Serial Flash
PDF  94 Pages
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Produttore elettronici  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Homepage  http://www.gigadevice.com/
Logo GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD25S513MDFEG Scheda tecnica(HTML) 37 Page - GigaDevice Semiconductor (Beijing) Inc.

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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25S513MD
37
8.14. Dual I/O Fast Read (DIOFR BBH or 4DIOFR BCH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input
the 3-Byte address (A23-
0) and a “Read Mode” Byte 2-bit per clock by SI and SO, and each bit being latched in on the
rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence
is shown in followed Figure25. The first Byte addressed can be at any location. The address is automatically incremented
to the next higher address in a single GD25B257D after each Byte of data is shifted out.
Figure 25 Dual I/O Fast Read Sequence Diagram (ADS=0)
Figure 26 Dual I/O Fast Read Sequence Diagram (ADS=1)
Command
0
1
2
3
4
5
6
7
BBH
CS#
SCLK
SI(IO0)
SO(IO1)
8
9 10 11 12 13 14 15
6
4
2
0
6
4
2
0
16 17 18 19 20 21 22 23
6
4
2
0
6
4
7
5
3
1
7
5
3
1
7
5
3
1
7
5
A23-16
A15-8
A7-0
M7-4
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SI(IO0)
SO(IO1)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
SCLK
6
7
Byte1
Byte2
Byte3
Byte4
2
0
3
1
M3-0
Command
0
1
2
3
4
5
6
7
BBH
CS#
SCLK
SI(IO0)
SO(IO1)
8
9 10 11 12 13 14 15
6
4
2
0
6
4
2
0
16 17 18 19 20 21 22 23
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
A31-24
A15-8
A7-0
CS#
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SI(IO0)
SO(IO1)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
SCLK
6
7
Byte1
Byte2
Byte3
Byte4
6
4
7
5
M7-4
24 25 26 27
6
4
2
0
7
5
3
1
A23-16
2
0
3
1
M3-0



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