GD25S513MDFEG datasheet(40/94 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25S513MD

8.16.

Quad I/O DTR Read (DTRQIO) (EEH or EDH)

The DTRQIO instruction enables Double Transfer Rate throughput on quad I/O of Serial Flash in read mode. The

address (interleave on 4 I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on 4 I/O pins) shift

out on both rising and falling edge of SCLK. The 8-bit address can be latched-in at one clock, and 8-bit data can be read

out at one clock, which means four bits at rising edge of clock, the other four bits at falling edge of clock. The first address

Byte can be at any location. The address is automatically increased to the next higher address in a single GD25B257D after

each Byte data is shifted out, so the whole memory of single GD25B257D can be read out at a single DTRQIO instruction.

The address counter rolls over to 0 when the highest address has been reached. Once writing DTRQIO instruction, the

following address/dummy/data out will perform as 8-bit instead of previous 1-bit.

While Program/Erase/Write Status Register cycle is in progress, DTRQIO instruction is rejected without any impact on

the Program/Erase/Write Status Register current cycle

Figure 31. DTR Quad I/O Fast Read Sequence Diagram (ADS=0)

Figure 32. DTR Quad I/O Fast Read Sequence Diagram (ADS=1)

High-Z

EDH

CS#

SCLK

IO0

IO1

9 10 11

18 19

4 0 4 0 4 0 4 0

4 0 4 0

5 1 5 1 5 1 5 1

5 1 5 1

A23-0

6 2 6 2 6 2 6 2

6 2 6 2

7 3 7 3 7 3 7 3

7 3 7 3

IO2

Dummy

Byt e1

Byte2

M7-0

DQS

IO3

Command

EDH

CS#

SCLK

IO0

IO1

9 10 11

19 20

4 0 4 0 4 0 4 0

4 0 4 0

5 1 5 1 5 1 5 1

5 1 5 1

A31-0

6 2 6 2 6 2 6 2

6 2 6 2

7 3 7 3 7 3 7 3

7 3 7 3

IO2

Byt e1

Byte2

M7-0

DQS

IO3

4 0

5 1

6 2

7 3

High-Z

Dummy

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