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GD25S513MDFEG Scheda tecnica(PDF) 5 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25S513MDFEG Scheda tecnica(HTML) 5 Page - GigaDevice Semiconductor (Beijing) Inc. |
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5 / 94 page ![]() 3.3V Uniform Sector Dual and Quad Serial Flash GD25S513MD 5 2. GENERAL DESCRIPTION The GD25S513MD (2 x 256M-bit) Serial MCP (Multi Chip Package) Flash memory is based on the popular GD25B series by stacking two individual GD25B257D dies into a standard 8-pin package. It offers the highest memory density for the low pin-count package, as well as Concurrent Operations in Serial Flash memory for applications that demand high Program/Erase data throughput. The GD25S513MD Serial flash supports the standard Serial Peripheral Interface (SPI), and the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2, and I/O3. The Dual SPI data is transferred with speed of 208Mbit/s, the Quad SPI data is transferred with speed of 416Mbit/s, and the DTR Quad I/O data is transferred with speed of 640Mbits/s. CONNECTION DIAGRAM Figure 1 Connection Diagram Note: 1. Only for special order, Pin 3 of 16-LEAD SOP package or Pin A4 of 24-BALL TFBGA (5x5 ball array) package is RESET# pin. Please contact GigaDevice for detail. 2. CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on. CS# SO (IO1) IO2 VSS Top View VCC IO3 SCLK SI (IO0) 8–LEAD WSON 1 2 3 4 5 6 7 8 Top View A2 A3 A4 A5 B2 B3 B4 B5 B1 C1 C2 C3 C4 C5 D1 D2 D3 D4 D5 E1 E2 E3 E4 E5 NC NC NC NC ECS# IO3 NC IO2 VCC NC (1) SI(IO0) NC DQS VSS NC SO(IO1) NC CS# SCLK NC NC NC NC NC 24-BALL TFBGA (5x5 ball array) CS# SO (IO1) IO2 VSS Top View VCC IO3 SCLK SI (IO0) 16-LEAD SOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NC (1) NC NC NC NC NC DQS NC |
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