GD25S513MDFEG datasheet(4/94 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25S513MD

1. FEATURES

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2 x 256M-bit Serial Flash

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Fast Program/Erase Speed

- 2 x 32M-Byte

- Page Program time: 0.4ms typical

- 256-Byte per programmable page

- Sector Erase time: 70ms typical

- Block Erase time: 0.16/0.22s typical

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Standard, Dual, Quad SPI, DTR

- Chip Erase time: 70s typical (single die)

- Standard SPI: SCLK, CS#, SI, SO, RESET#

- Dual SPI: SCLK, CS#, IO0, IO1, RESET#

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Flexible Architecture

- Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3

- Uniform Sectors of 4K-Byte

- SPI DTR (Double Transfer Rate) Read

- Uniform Blocks of 32/64K-Byte

- On-chip ECC (1-bit correction every 8-Byte) (1)

- 3 or 4-Byte Addressing Mode

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Low Power Consumption

- 2uA typical deep power down current

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High Speed Clock Frequency

- 24uA typical standby current

- Maximum 104MHz for fast read on 3.0 - 3.6V power supply

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Dual I/O Data transfer up to 208Mbits/s

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Advanced Security Feature

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Quad I/O Data transfer up to 416Mbits/s

- 6x2048-Byte Security Registers With OTP Locks

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DTR Quad I/O Data transfer up to 640Mbits/s

- 128-bit Unique ID

for individual die

- Maximum 80MHz for fast read on 2.7 - 3.0V power supply

- Serial Flash Discoverable parameters (SFDP) register

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Dual I/O Data transfer up to 160Mbits/s

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Quad I/O Data transfer up to 320Mbits/s

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Single Power Supply Voltage

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DTR Quad I/O Data transfer up to 560Mbits/s

- Full voltage range: 2.7 - 3.6V

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Software Write Protection

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Cycling Endurance and Data Retention

- Write protect all/portion of memory via software

- Minimum 100,000 Program/Erase Cycles

- Top/Bottom Block protection

- 20-year data retention typical

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Flexible “Concurrent Operation”

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Package Information

- Independent single die access

- SOP16 (300mil)

Allows “Read while Program/Erase”

- WSON8 (8x6mm)

Allows “Multi Die Program/Erase”

- TFBGA-24 (5x5 ball array)

- Improves Program/Erase throughput

- Reduces Suspend/Resume activities

Note:

1. When ECC is enabled, it is required to program minimum one or multiple aligned 8-Byte granularities. Every aligned 8-

Byte granularity should only be programmed once before Erase to ensure correct ECC operations.

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