GD25S513MDFEG datasheet(11/94 Pages) GIGADEVICE

11 / 94 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25S513MD

4.2.

SPI Mode

Standard SPI

The GD25S513MD features a serial peripheral interface on 4 signals buses: Serial Clock (SCLK), Chip Select (CS#),

Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the

rising edge of SCLK and data shifts out on the falling edge of SCLK.

Dual SPI

The GD25S513MD

supports Dual SPI operation when using the “Dual Output Fast Read”, “Dual Output Fast Read

with 4-

Byte address”, “Dual I/O Fast Read” and “Dual I/O Fast Read with 4-Byte address” commands (3BH 3CH BBH and

BCH). These commands allow data to be transferred to or from the device at twice the rate of the standard SPI. When using

the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.

Quad SPI

The GD25S513MD supports Quad SPI operation when usi

ng the “Quad Output Fast Read”, “Quad Output Fast Read

with 4-

Byte address”, “Quad I/O Fast Read”, “Quad I/O Fast Read with 4-Byte address” (6BH, 6CH, EBH and ECH)

commands. These commands allow data to be transferred to or from the device at four times the rate of the standard SPI.

When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, in addition to IO2 and

IO3 pins. For GD25S513MD, QE bit is set to 1 as default and cannot be changed.

DTR Quad SPI

The GD25S513MD

supports DTR Quad SPI operation when using the “DTR Quad I/O Fast Read” (EDH and EEH)

command.

These command allow data to be transferred to or from the device at eight times the rate of the standard SPI, and data

output will be latched on both rising and falling edges of the serial clock. When using the DTR Quad SPI command the SI

and SO pins become bidirectional I/O pins: IO0 and IO1, in addition to IO2 and IO3 pins.

4.3.

ECC Function

The ECC Correction Signal (ECS#) pin is provided to the system hardware designers to determine the ECC status

during any Read operation. When the internal ECC engine is disabled (ECC=0 in Status Register), the ECS# pin is also

disabled. When ECC is enabled (ECC=1 in Status Register), the ECS# pin will be pulled low during any 8-Byte Read data

output period in which an ECC event has occurred. Depending on the ECS bit setting in the Extended Address Register,

ECS# pin can be used to represent either SEC (Single Error Correction) or DED (Double Error Detection). ECC Correction

Signal (ECS#) pin is an Open-Drain connection.

GD25S513MDFEG Scheda tecnica(PDF) 11 Page - GigaDevice Semiconductor (Beijing) Inc.