GD25S513MDFEG datasheet(42/94 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25S513MD

8.17. Write Data Learning Pattern (4AH)

For Quad DTR Read commands, a pre-

defined “Data Learning Pattern” can be used by the flash memory controller

to determine the flash data output timing on 4 I/O pins. When DLP=1, during the last 4 dummy clocks just prior to the data

output, GD25B257

D will output “00110100” Data Learning Pattern sequence on each of the 4 I/O pins. During this period,

controller can fine tune the data latching timing for each I/O pins to achieve optimum system performance. DLP=0 will

disable the Data Learning Pattern output.

Figure 34. Data Learning Pattern Output Sequence Diagram

The Data Learning Pattern can also be defined by a “Write Data Learning Pattern (4AH)” command followed by 8-bit

user-defined pattern. The user defined pattern is volatile. After device power cycle, the Data Learning Pattern will return to

its “00110100” default value.

Figure 35. Write Data Learning Pattern Sequence Diagram

Command

EDH

CS#

SCLK

SI(IO0)

SO(IO1)

9 10 11 12 13 14 15 16 17 18 19 20 21

A23-0

IO2

IO3

Data

Learning

Pattern

23 19 15 11

22 18 14 10

21 17 13

20 16 12

Byte1Byte2Byte3

M7-0

Command

4AH

CS#

SCLK

High-Z

9 10 11 12 13 14 15

MSB

Data Learning Ptn.

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