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GD25S513MDFEG Scheda tecnica(PDF) 38 Page - GigaDevice Semiconductor (Beijing) Inc.

Il numero della parte GD25S513MDFEG
Spiegazioni elettronici  3.3V Uniform Sector Dual and Quad Serial Flash
PDF  94 Pages
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Produttore elettronici  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Homepage  http://www.gigadevice.com/
Logo GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD25S513MDFEG Scheda tecnica(HTML) 38 Page - GigaDevice Semiconductor (Beijing) Inc.

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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25S513MD
38
Figure 27 Dual I/O Fast Read with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1)
8.15.
Quad I/O Fast Read (QIOFR EBH or 4QIOFR ECH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the
3-Byte address (A23-
0) and a “Read Mode” Byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO2, IO3, and each bit
being latched in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1,
IO2, IO3. The first Byte addressed can be at any location. The address is automatically incremented to the next higher
address in a single GD25B257D after each Byte of data is shifted out.
Figure 28 Quad I/O Fast Read Sequence Diagram (ADS=0)
Command
0
1
2
3
4
5
6
7
EBH
CS#
SCLK
SI(IO0)
SO(IO1)
8
9 10 11 12 13 14 15
4
0
4
0
4
0
4
0
16 17 18 19 20 21 22 23
4
0
4
0
5
1
5
1
5
1
5
1
5
1
5
1
A23-16 A15-8 A7-0
M7-0
6
2
6
2
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
3
7
3
7
3
IO2
IO3
4
5
6
7
Dummy
Byte1 Byte2
Command
0
1
2
3
4
5
6
7
BCH
CS#
SCLK
SI(IO0)
SO(IO1)
8
9 10 11 12 13 14 15
6
4
2
0
6
4
2
0
16 17 18 19 20 21 22 23
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
A31-24
A15-8
A7-0
CS#
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SI(IO0)
SO(IO1)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
SCLK
6
7
Byte1
Byte2
Byte3
Byte4
6
4
7
5
M7-4
24 25 26 27
6
4
2
0
7
5
3
1
A23-16
2
0
3
1
M3-0



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