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GD25S513MDFEG Scheda tecnica(PDF) 85 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25S513MDFEG Scheda tecnica(HTML) 85 Page - GigaDevice Semiconductor (Beijing) Inc. |
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85 / 94 page  3.3V Uniform Sector Dual and Quad Serial Flash GD25S513MD 85 Table 32 AC CHARACTERISTICS (T= -40℃~125℃, VCC=2.7~3.6V, CL=30pf) Symbol Parameter Min. Typ. Max. Unit. fC Serial Clock Frequency for all instructions except Read 104 MHz fC1 Serial Clock Frequency for Dual I/O (BBH, BCH), Quad I/O (EBH, ECH),Dual Output (3BH, 3CH), Quad Output (6BH, 6CH), Fast Read (0BH, 0CH) instructions, on 3.0 – 3.6V power supply 104 MHz fC2 Serial Clock Frequency for DTR Quad I/O Fast Read (EEH, EDH) instructions, on 3.0 - 3.6V power supply 80 MHz fC3 Serial Clock Frequency for Dual I/O (BBH, BCH), Quad I/O (EBH, ECH), Dual Output (3BH, 3CH), Quad Output (6BH, 6CH), Fast Read (0BH, 0CH) instructions, on 2.7 – 3.0V power supply 80 MHz fC4 Serial Clock Frequency for DTR Quad I/O Fast Read (EEH, EDH) instructions, on 2.7 – 3.0V power supply 70 MHz fR Serial Clock Frequency For: Read (03H, 13H) 50 MHz tCLH1 Serial Clock High Time in STR Mode 3.7 ns tCLH2 Serial Clock High Time in DTR Mode 5.6 ns tCLL1 Serial Clock Low Time in STR Mode 3.7 ns tCLL2 Serial Clock Low Time in DTR Mode 5.6 ns tCLCH Serial Clock Rise Time (Slew Rate) 0.2 V/ns tCHCL Serial Clock Fall Time (Slew Rate) 0.2 V/ns tSLCH CS# Active Setup Time 8 ns tCHSH CS# Active Hold Time 5 ns tSHCH CS# Not Active Setup Time 5 ns tCHSL CS# Not Active Hold Time 5 ns tSHSL CS# High Time (Read/Write) 20 ns tSHQZ Output Disable Time 6 ns tCLQX Output Hold Time 1.8 ns tDVCH Data In Setup Time 2 ns tCHDX Data In Hold Time 2 ns tCLQV Clock Low To Output Valid 7 ns tDP CS# High To Deep Power-Down Mode 20 μs tRES1 CS# High To Standby Mode Without Electronic Signature Read 30 μs tRES2 CS# High To Standby Mode With Electronic Signature Read 30 μs tSUS Cs# High To Next Command After Suspend 20 μs tRS Latency Between Resume And Next Suspend 100 μs tRST CS# High To Next Command After Reset (Except From Erase) 30 μs tRST_E CS# High To Next Command After Reset (From Erase) 12 ms tW Write Status Register Cycle Time 5 20 ms tBP1 Byte Program Time (First Byte) 30 60 μs tBP2 Additional Byte Program Time (After First Byte) 2.5 15 μs tPP Page Programming Time 0.4 2.5 ms tSE Sector Erase Time 70 450 ms |
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