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H8S/2218 Scheda tecnica(PDF) 235 Page - Renesas Technology Corp |
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H8S/2218 Scheda tecnica(HTML) 235 Page - Renesas Technology Corp |
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235 / 750 page ![]() Section 7 DMA Controller (DMAC) Rev.6.00 Jun. 03, 2008 Page 187 of 698 REJ09B0074-0600 Figure 7.8 illustrates operation in normal mode. Address T A Address B A Transfer Address T B Notes: Address T A = LA Address T B = LB Address B A = LA + SAIDE · (–1) SAID · (2DTSZ · (N–1)) Address B B = LB + DAIDE · (–1) DAID · (2DTSZ · (N–1)) L A = Value set in MARA L B = Value set in MARB N = Value set in ETCRA Address B B Figure 7.8 Operation in Normal Mode Transfer requests (activation sources) are external requests and auto-requests. With auto-request, the DMAC is only activated by register setting, and the specified number of transfers are performed automatically. With auto-request, cycle steal mode or burst mode can be selected. In cycle steal mode, the bus is released to another bus master each time a transfer is performed. In burst mode, the bus is held continuously until transfer ends. For setting details, see section 7.3.4, DMA Controller Register (DMACR). |
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