H8SSLASH2218 datasheet(239/750 Pages) RENESAS

Il numero della parte	H8S/2218

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	750 Pages

Scroll/Zoom	100%

Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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239 / 750 page

Section 7 DMA Controller (DMAC)

Rev.6.00 Jun. 03, 2008 Page 191 of 698

REJ09B0074-0600

Figure 7.11 illustrates operation in block transfer mode when MARA is designated as a block area.

Address T

Address B

Transfer

Address T

Notes:

Address T

A = LA

Address T

B = LB

Address B

A = LA + SAIDE · (–1)

SAID · (2DTSZ · (N–1))

Address B

B = LB + DAIDE · (–1)

DAID · (2DTSZ · (M · N–1))

LA = Value set in MARA

LB = Value set in MARB

N = Value set in ETCRB

M = Value set in ETCRAH and ETCRAL

Address B

1st block

2nd block

Nth block

Block area

Consecutive transfer

of M bytes or words

is performed in

response to one

request

Figure 7.11 Operation in Block Transfer Mode (BLKDIR = 1)

ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a

single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00.

ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register

for which a block designation has been given by the BLKDIR bit in DMACRA is restored in

accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.

H8S/2218 Scheda tecnica(PDF) 239 Page - Renesas Technology Corp