H8SSLASH2218 datasheet(236/750 Pages) RENESAS

236 / 750 page

Section 7 DMA Controller (DMAC)

Rev.6.00 Jun. 03, 2008 Page 188 of 698

REJ09B0074-0600

Figure 7.9 shows an example of the setting procedure for normal mode.

Normal mode

setting

Set DMABCRH

Set transfer source

and transfer destination

addresses

Set number of transfers

Set DMACR

Read DMABCRL

Set DMABCRL

Normal mode

[1]

[2]

[3]

[4]

[5]

[6]

[1] Set each bit in DMABCRH.

· Set the FAE bit to 1 to select full address

mode.

· Specify enabling or disabling of internal

interrupt clearing with the DTA bit.

[2] Set the transfer source address in MARA, and

the transfer destination address in MARB.

[3] Set the number of transfers in ETCRA.

[4] Set each bit in DMACRA and DMACRB.

· Set the transfer data size with the DTSZ bit.

· Specify whether MARA is to be

incremented, decremented, or fixed, with

the SAID and SAIDE bits.

· Clear the BLKE bit to 0 to select normal

mode.

· Specify whether MARB is to be

incremented, decremented, or fixed, with

the DAID and DAIDE bits.

· Select the activation source with bits DTF3

to DTF0.

[5] Read the DTE = 0 and DTME = 0 in

DMABCRL.

[6] Set each bit in DMABCRL.

· Specify enabling or desabling of transfer

end interrupts with the DTIE bit.

· Set both the DTME bit and the DTE bit to 1

to enable transfer.

Figure 7.9 Example of Normal Mode Setting Procedure

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