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H8S/2218 Scheda tecnica(PDF) 238 Page - Renesas Technology Corp |
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H8S/2218 Scheda tecnica(HTML) 238 Page - Renesas Technology Corp |
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238 / 750 page ![]() Section 7 DMA Controller (DMAC) Rev.6.00 Jun. 03, 2008 Page 190 of 698 REJ09B0074-0600 Figure 7.10 illustrates operation in block transfer mode when MARB is designated as a block area. Address T A Address B A Transfer Address T B Notes: Address T A = LA Address T B = LB Address B A = LA + SAIDE · (–1) SAID · (2DTSZ · (M · N–1)) Address B B = LB + DAIDE · (–1) DAID · (2DTSZ · (N–1)) L A = Value set in MARA L B = Value set in MARB N = Value set in ETCRA M = Value set in ETCRAH and ETCRAL Address B B 1st block 2nd block Nth block Block area Consecutive transfer of M bytes or words is performed in response to one request Figure 7.10 Operation in Block Transfer Mode (BLKDIR = 0) |
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