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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8S/2218 Scheda tecnica(PDF) 240 Page - Renesas Technology Corp |
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H8S/2218 Scheda tecnica(HTML) 240 Page - Renesas Technology Corp |
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240 / 750 page  Section 7 DMA Controller (DMAC) Rev.6.00 Jun. 03, 2008 Page 192 of 698 REJ09B0074-0600 ETCRB is decremented by 1 every block transfer, and when the count reaches H'0000 the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this point, an interrupt request is sent to the CPU. Figure 7.12 shows the operation flow in block transfer mode. Start (DTE = DTME = 1) MARA = MARA – SAIDE · (–1)SAID · 2DTSZ · ETCRAH No Yes No Yes No Yes No Yes Clear DTE bit to 0 to end transfer Acquire bus ETCRAL = ETCRAL–1 Transfer request? ETCRAL = H'00 Release bus BLKDIR = 0 ETCRAL = ETCRAH ETCRB = ETCRB – 1 ETCRB = H'0000 Read address specified by MARA MARA = MARA + SAIDE · (–1)SAID · 2DTSZ Write to address specified by MARB MARB = MARB + DAIDE · (–1)DAID · 2DTSZ MARB = MARB – DAIDE · (–1)DAID · 2DTSZ · ETCRAH Figure 7.12 Operation Flow in Block Transfer Mode |
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