ATtiny261-ESSZ datasheet(136/227 Pages) ATMEL

136 / 227 page

136

7753C–AVR–07/09

ATtiny261/ATtiny461/ATtiny861

17.5.2

USIBR – USI Buffer Register

The content of the Serial Register is loaded to the USI Buffer Register when the transfer is com-

pleted, and instead of accessing the USI Data Register (the Serial Register) the USI Data Buffer

can be accessed when the CPU reads the received data. This gives the CPU time to handle

other program tasks too as the controlling of the USI is not so timing critical. The USI flags as set

same as when reading the USIDR register.

17.5.3

USISR – USI Status Register

The Status Register contains Interrupt Flags, line Status Flags and the counter value.

• Bit 7 – USISIF: Start Condition Interrupt Flag

When Two-wire mode is selected, the USISIF Flag is set (to one) when a start condition is

detected. When output disable mode or Three-wire mode is selected and (USICSx = 0b11 &

USICLK = 0) or (USICS = 0b10 & USICLK = 0), any edge on the SCK pin sets the flag.

An interrupt will be generated when the flag is set while the USISIE bit in USICR and the Global

Interrupt Enable Flag are set. The flag will only be cleared by writing a logical one to the USISIF

bit. Clearing this bit will release the start detection hold of USCL in Two-wire mode.

A start condition interrupt will wakeup the processor from all sleep modes.

• Bit 6 – USIOIF: Counter Overflow Interrupt Flag

This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). An

interrupt will be generated when the flag is set while the USIOIE bit in USICR and the Global

Interrupt Enable Flag are set. The flag will only be cleared if a one is written to the USIOIF bit.

Clearing this bit will release the counter overflow hold of SCL in Two-wire mode.

A counter overflow interrupt will wake up the processor from Idle sleep mode.

• Bit 5 – USIPF: Stop Condition Flag

When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is detected.

The flag is cleared by writing a one to this bit. Note that this is not an Interrupt Flag. This signal is

useful when implementing Two-wire bus master arbitration.

• Bit 4 – USIDC: Data Output Collision

This bit is logical one when bit 7 in the USI Data Register differs from the physical pin value. The

flag is only valid when Two-wire mode is used. This signal is useful when implementing

Two-wire bus master arbitration.

• Bits 3:0 – USICNT3..0: Counter Value

These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or

written by the CPU.

Bit

0x10 (0x30)

MSB

LSB

USIBR

Read/Write

Initial Value

Bit

654

0x0E (0x2E)

USISIF

USIOIF

USIPF

USIDC

USICNT3

USICNT2

USICNT1

USICNT0

USISR

Read/Write

R/W

Initial Value

ATtiny261-ESSZ Scheda tecnica(PDF) 136 Page - ATMEL Corporation

ATtiny261-ESSZ Scheda tecnica(HTML) 136 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL