ATtiny261-ESSZ datasheet(138/227 Pages) ATMEL

138 / 227 page

138

7753C–AVR–07/09

ATtiny261/ATtiny461/ATtiny861

Note:

1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively

to avoid confusion between the modes of operation.

• Bit 3:2 – USICS1:0: Clock Source Select

These bits set the clock source for the USI Data Register and counter. The data output latch

ensures that the output is changed at the opposite edge of the sampling of the data input

(DI/SDA) when using external clock source (USCK/SCL). When software strobe or

Timer/Counter0 Compare Match clock option is selected, the output latch is transparent and

therefore the output is changed immediately. Clearing the USICS1:0 bits enables software

strobe option. When using this option, writing a one to the USICLK bit clocks both the USI Data

used as a strobe, but selects between external clocking and software clocking by the USITC

strobe bit.

Table 17-2 on page 139 shows the relationship between the USICS1..0 and USICLK setting and

clock source used for the USI Data Register and the 4-bit counter.

Table 17-1.

Relations between USIWM1..0 and the USI Operation

USIWM1

USIWM0 Description

Outputs, clock hold, and start detector disabled. Port pins operates as normal.

Three-wire mode. Uses DO, DI, and USCK pins.

The Data Output (DO) pin overrides the corresponding bit in the PORT Register in

this mode. However, the corresponding DDR bit still controls the data direction.

When the port pin is set as input the pins pull-up is controlled by the PORT bit.

The Data Input (DI) and Serial Clock (USCK) pins do not affect the normal port

operation. When operating as master, clock pulses are software generated by

toggling the PORT Register, while the data direction is set to output. The USITC

bit in the USICR Register can be used for this purpose.

Two-wire mode. Uses SDA (DI) and SCL (USCK) pins(1).

The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and uses

open-collector output drives. The output drivers are enabled by setting the

corresponding bit for SDA and SCL in the DDR Register.

When the output driver is enabled for the SDA pin, the output driver will force the

line SDA low if the output of the USI Data Register or the corresponding bit in the

PORT Register is zero. Otherwise the SDA line will not be driven (i.e., it is

released). When the SCL pin output driver is enabled the SCL line will be forced

low if the corresponding bit in the PORT Register is zero, or by the start detector.

Otherwise the SCL line will not be driven.

The SCL line is held low when a start detector detects a start condition and the

output is enabled. Clearing the Start Condition Flag (USISIF) releases the line.

The SDA and SCL pin inputs is not affected by enabling this mode. Pull-ups on the

SDA and SCL port pin are disabled in Two-wire mode.

Two-wire mode. Uses SDA and SCL pins.

Same operation as for the Two-wire mode described above, except that the SCL

line is also held low when a counter overflow occurs, and is held low until the

Counter Overflow Flag (USIOIF) is cleared.

ATtiny261-ESSZ Scheda tecnica(PDF) 138 Page - ATMEL Corporation

ATtiny261-ESSZ Scheda tecnica(HTML) 138 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL